|
Session 1A - Innovations in In-Memory Computing for AI and High-Performance Hardware
Chair: TBD, TBD Co-Chair: TBD, TBD |
| 10:40 |
Session 1A -
1A.2:
ReAD: ReRAM-Based Computing-In-Memory Design and Optimization by AC/DC Mixed Signal
Guanyu Chi1, Markus Leibl1, Qingrong Huang2, Xunzhao Yin2, Bing Li3, Ulf Schlichtmann1 1Technical University of Munich, 2Zhejiang University, 3University of Siegen |
| 11:00 |
Session 1A -
1A.3:
In-Memory Template Matching with Approximated PCC Computation Leveraging Memristive System
Sree Nirmillo Biswash Tushar1, Sk Hasibul Alam1, Graham Buchanan1, Rocco Febbo1, Hritom Das2, Garrett S. Rose1 1University of Tennessee, Knoxville, 2Oklahoma State University |
| 11:20 |
Session 1A -
1A.4:
An Error-resilient Compute-in-memory 3D FPCA Architecture for High-performance Floating-point Operations
Hasita Veluri and Dilip Vasudevan Lawrence Berkeley National Laboratory |
| 11:40 |
Session 1A -
1A.5:
HIDE: A Hyperdimensional In-DRAM Encoder for Fast and Energy-Efficient Classification
Ahmed Mamdouh and Dayane Reis University of South Florida |
|
Session 1B - Security Primitives in Modern Designs
Chair: TBD, TBD |
| 10:20 |
Session 1B -
1B.1:
XORed Carry Chain Ring Oscillator Factored True Random Number Generator
Kanish R1 and Madhav Rao2 1International Institute of Information Technology Bangalore, 2International Institute of Information Technology-Bangalore |
| 10:40 |
Session 1B -
1B.2:
Non-Homogeneous Composite Karatsuba Multipliers Factored Hardware-Efficient ECDSA Generation and Verification Accelerator Units
Pruthvi Parate1, Alwin Shaju1, Sanampudi Gopala Krishna Reddy1, Vasanthi D R1, Madhav Rao2 1International Institute of Information Technology Bangalore, 2International Institute of Information Technology-Bangalore |
| 11:00 |
Session 1B -
1B.3:
Device Boot-up Security Restoration with Post-Quantum Split-key KEM
Joonas Ahola, Jan-Erik Ekberg, Sampo Sovio Huawei Technologies Oy |
| 11:20 |
Session 1B -
1B.4:
Quantum Data Breach: Reusing Training Dataset by Untrusted Quantum Clouds
Suryansh Upadhyay1 and Swaroop Ghosh2 1Penn State University, 2Pennsylvania State University |
|
Session 1C - Design Verification and High-Speed Memory Testing
Chair: Chidhambaraanathan R, Synopsys Inc, Sunnyvale Co-Chair: Sumit Jha, Professor, FIU, Miami |
| 10:20 |
Session 1C -
1C.1:
AutoFlows: Inferring Message Flows From System Communication Traces
Bardia Nadimi and Hao Zheng University of South Florida |
| 10:40 |
Session 1C -
1C.2:
Automated Verilog Assertion Generation Using Fine-Tuned LLMs with Subtask-Specific Iterative Prompting
Mohammad Shahidzadeh1, Behnam Ghavami1, Steve Wilton2, Lesley Shannon1 1Simon Fraser University, 2University of British Columbia |
| 11:00 |
Session 1C -
1C.3:
Leveraging DDR5 RCDs for High-Speed DDR5 Protocol Analysis: A Novel Approach to RDIMM Testing
Xinran Li Professional |
| 11:20 |
Session 1C -
1C.4:
Formal Verification of a Custom Compiler for a Fully Homomorphic Encryption Accelerator
Zhenkun Yang1, Suvadeep Banerjee2, Jeremy Casas1, Jin Yang1 1Intel Corporation, 2Intel Labs, Intel |
|
Session 2A - Generative AI and its Application to Design Automation
Chair: TBD, TBD Co-Chair: TBD, TBD |
| 13:30 |
Session 2A -
2A.1:
EDA-Debugger: A Large Language Model-based Expert for Automated EDA Issue Resolution
Junyan Li1, Gwok-Waa Wan2, Sam-Zaak Wong2, Xi Wang1 1Southeast University, 2NCTIEDA |
| 13:50 |
Session 2A -
2A.2:
VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency
Zhuorui Zhao1, Ruidi Qiu1, Ing-Chao Lin2, Grace Li Zhang3, Bing Li4, Ulf Schlichtmann1 1Technical University of Munich, 2National Cheng Kung University, 3TU Darmstadt, 4University of Siegen |
| 14:10 |
Session 2A -
2A.3:
Paradigm-Based Automatic HDL Code Generation Using LLMs
Wenhao Sun1, Bing Li2, Grace Li Zhang3, Xunzhao Yin4, Cheng Zhuo4, Ulf Schlichtmann1 1Technical University of Munich, 2University of Siegen, 3TU Darmstadt, 4Zhejiang University |
| 14:30 |
Session 2A -
2A.4:
Toward Automated Potential Primary Asset Identification in Verilog Designs
Subroto Nath and Benjamin Tan University of Calgary |
|
Session 2B - Security-aware Design Flow for Integeretaed Circuits
Chair: TBD, TBD |
| 13:30 |
Session 2B -
2B.1:
FlexGuard: Dynamic Scoring \& Stochastic Routing for Balanced Security-Performance in 3D NoCs
Mahdi Hasanzadeh1, Ebad Taheri2, Jason Green1, Abdolhossein Sarrafzadeh1, Ahmad Patooghy1 1North Carolina A & T State University, 2Hewlett Packard Labs |
| 13:50 |
Session 2B -
2B.2:
REDACTOR: eFPGA Redaction for DNN Accelerator Security
Yazan Baddour, Ava Hedayatipour, Amin Rezaei California State University, Long Beach |
| 14:10 |
Session 2B -
2B.3:
Power and Area-Efficient ECC Processor with Sequential Recursive Polynomial Multiplier Implementation
Pruthvi Parate1, Alwin Shaju1, Vasanthi D R1, Madhav Rao2 1International Institute of Information Technology Bangalore, 2International Institute of Information Technology-Bangalore |
| 14:30 |
Session 2B -
2B.4:
A PPA- and Security-aware Physical Design Flow
Chun-Wei Chiu and Ting-Chi Wang National Tsing Hua University |
| 14:50 |
Session 2B -
2B.5:
The Impact of Logic Locking on Confidentiality: An Automated Evaluation
Lennart M. Reimann1, Evgenii Rezunov1, Dominik Germek2, Luca Collini3, Christian Pilato4, Ramesh Karri5, Rainer Leupers1 1RWTH Aachen University, 2Corporate Research Robert Bosch GmbH, 3NYU Tandon School of Engineering, 4Politecnico di Milano, 5NYU |
|
Session 2C - Efficient Hardware Architectures for AI and Approximate Computing
Chair: TBD, TBD |
| 13:30 |
Session 2C -
2C.1:
Efficient Self-Supervised Continual Learning with Progressive Task-correlated Layer Freezing
Li Yang1, Sen Lin2, Fan Zhang3, Junshan Zhang4, Deliang Fan5 1university of north carolina at charlotte, 2University of Houston, 3Johns Hopkins University, 4University of California, Davis, 5Arizona State University |
| 13:50 |
Session 2C -
2C.2:
Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators
Yuhao Liu1, Salim Ullah2, Akash Kumar2 1Technische Universitaet Dresden, 2Ruhr-Universitaet Bochum |
| 14:10 |
Session 2C -
2C.3:
LibApprox: A Comprehensive Library for Performance Efficient Approximate Circuits
Bhargav D V1, Dantu Nandini Devi2, Rachana Kaparthi1, Madhav Rao1 1International Institute of Information Technology-Bangalore, 2International Institute of Information Technology Bangalore |
| 14:30 |
Session 2C -
2C.4:
Meta-Heuristic Optimization for Designing Error Diluted Weight Stationary Approximate Systolic Array Architecture
Dantu Nandini Devi1, Bindu G Gowda2, Madhav Rao3 1International Institute of Information Technology Bangalore, 2International Institute of Information Technology, Bangalore, 3International Institute of Information Technology-Bangalore |
| 14:50 |
Session 2C -
2C.5:
Design of Hardware-Efficient Inexact Multiplier Using Evolutionary Algorithm Factored by Multi-variate Approximation
Dantu Nandini Devi1, Saketh Gajawada2, Madhav Rao3 1International Institute of Information Technology Bangalore, 2InternationalInstituteofInformationTechnologyBangalore, 3International Institute of Information Technology-Bangalore |
|
Session PW1 - Short Presentation & WIP Session 1
Chair: Cindy Yang Yi, Virginia Tech |
| 9:40 |
Session PW1 -
PW1.1:
Area-optimized 2D Interleaved Adder Tree Design for Sparse DCIM Edge Processing
Akash Sankhe1, Mukul Lokhande1, Radheshyam Sharma1, Santosh Vishvakarma2 1Indian Institute of Technology Indore, 2IIT Indore |
| 9:45 |
Session PW1 -
PW1.2:
Hardware and Algorithm Codesign for Efficient Gaze Tracking in Virtual Reality System
Sai Qian Zhang, Wenxuan Liu, Haiyu Wang New York University |
| 9:50 |
Session PW1 -
PW1.3:
Reinforcement Learning for Testtime Optimization in the Network-on-Chip based Systems
Anantha Ganesh Karikar Kamath1, Aditya Kulkarni2, Himanshu Singh2, Kanchan Manna3 1BITS Pilani, Goa Campus, 2Dept. of CSIS, BITS Pilani, Goa Campus, 3Dept. of CSIS, BITS Pilani Goa Campus |
| 9:55 |
Session PW1 -
PW1.4:
Efficient and Scalable Place and Route Methodology for Large-Scale Hierarchical Designs: Achieving Faster Turnaround Time and Predictability
Subhadeep Aich1, Rajanikant Sakariya2, Vivek Joshi1 1Texas Instruments, 2Texas Instruments (India) Pvt. Ltd. |
| 10:00 |
Session PW1 -
PW1.5:
Die Area Reduction by Decongesting Top Channels Using Novel Feedthrough Insertion Methodology in Hierarchical SoC Designs
Rajanikant Sakariya1, Subhadeep Aich1, Vivek Joshi1, Roger Griesmer2 1Texas Instruments (India) Pvt. Ltd., 2Texas Instruments Incorporated |
| 10:05 |
Session PW1 -
PW1.6:
DT2HDL: A Binary Decision Tree to HDL Generation tool
Qijia Tang, Dinesh Pamunuwa, Roshan Weerasekera University of Bristol |
| 10:10 |
Session PW1 -
PW1.7:
Adding Context to LLM-Guided Verilog Repair
Abdelrahman Elnaggar and Benjamin Tan University of Calgary |
| 10:15 |
Session PW1 -
PW1.8:
A Max Weighted Matching based Post-HLS Power Gating with Comprehensive Power Modeling
Xiuyan Zhang and Shantanu Dutt University of Illinois at Chicago |
| 10:20 |
Session PW1 -
PW1.9:
Therunet-SP: 2.5D IC Thermal Simulation Using U-Net Convolution and Scaling Procedure
Yu-Min Lee, Shun-Ping Huang, Ying-Hui Lin National Yang Ming Chiao Tung University |
| 10:25 |
Session PW1 -
PW1.10:
MErBAG: Mesh Error Based Adaptive Grid Generation in System-Level Thermal Analysis
Yu-Min Lee, Shih-Chieh Hsu, Bo-Yi Tsai, Zong-Lin Lu National Yang Ming Chiao Tung University |
|
Session PW2 - Short Presentation & WIP Session 2
Chair: Hossein Sayadi, California State University, Long Beach |
| 9:40 |
Session PW2 -
PW2.1:
Illuminati: A Simulation Framework for Modeling and Evaluating Photonic Neural Networks
Andy Wolff and Avinash Karanth Ohio University |
| 9:45 |
Session PW2 -
PW2.2:
Evaluating LLM-based Communicative Agents for Verilog Design
Parker Link and Benjamin Tan University of Calgary |
| 9:50 |
Session PW2 -
PW2.3:
Weighted Vertex Cover Using Disjoint Set Data Structures for the Memory Reconfiguration Problem
Rouwaida Kanj Synopsys |
| 9:55 |
Session PW2 -
PW2.4:
Guardians of the Quantum GAN
Archisman Ghosh1, Debarshi Kundu2, Avimita Chatterjee2, Swaroop Ghosh2 1The Pennsylvania State University, 2Pennsylvania State University |
| 10:00 |
Session PW2 -
PW2.5:
Graphene-Based FPGA Design and Optimization at the 7nm FinFET Technology Node
Sheng Lu1, Zhenlin Pei1, Liuting Shang2, Sungyong Jung3, Qilian Liang2, Chenyun Pan2 1The University of Texas at Arlington, 2University of Texas at Arlington, 3South Dakota State University |
| 10:05 |
Session PW2 -
PW2.6:
Function Approximation Using Analog Building Blocks in Flexible Electronics
Paula Carolina Lozano Duarte1, Aradhana Dube1, Georgios Zervakis2, Mehdi Tahoori1, Sani R Nassif3 1Karlsruhe Institute of Technology, 2University of Patras, 3Radyalis |
| 10:10 |
Session PW2 -
PW2.7:
Deep Learning-Based ASM-ESD Forward I-V Parameter Extraction
Fredo Paraginog Chavez and Sourabh Khandelwal Macquarie University |
| 10:15 |
Session PW2 -
PW2.8:
Exploring Parallel Implementation of SPHINCS+ using Advanced Vector Extensions (AVX) Sets
Yaoyun Zhou1, Kavin Rajasekaran1, QIAN WANG2 1University of California, Merced, 2University of California Merced |
| 10:20 |
Session PW2 -
PW2.9:
Cross-Layer EM Fault Injection Assessment Framework
Hanqiu Wang1, Ruochen Dai1, Tuba Yavuz1, Xiaolong Guo2, Orlando Arias3, Dean Sullivan4, Siqi Dai1, Honggang Yu1, Michael Lee1, Domenic Forte1, Shuo Wang1 1University of Florida, 2Electrical and Computer Engineering Department, Kansas State University, 3University of Massachusetts Lowell, 4University of New Hampshire |
| 10:25 |
Session PW2 -
PW2.10:
Adversarial Assertions
Prabhat Mishra University of Florida |
| 10:30 |
Session PW2 -
PW2.11:
Aging Attack on Systolic Array-based AI accelerators via NBTI-Induced Aging
Masoud Heidary and Biresh Kumar Joardar University of Houston |
|
Session PW3 - Short Presentation & WIP Session 3
Chair: Deliang Fan, Johns Hopkins University |
| 9:40 |
Session PW3 -
PW3.1:
Optimizing Post-quantum Crypto Algorithms in Embedded IoT Systems with QUIC Protocol
Ben Dong1 and QIAN WANG2 1University of California, Merced, 2University of California Merced |
| 9:45 |
Session PW3 -
PW3.2:
Analysis of the Impact of LFSR Architecture on Accuracy of Stochastic Computing Processors
Seongmo An1, Sangho Lee2, Jinyoung Shin1, Yue Ri Jeong1, Seung Eun Lee1 1Seoul National University of Science and Technology, 2Seoul National University of Science and Technolgoy |
| 9:50 |
Session PW3 -
PW3.3:
A 17mV Load Transient, Highly Efficient Low Ripple Split-Inductor based Buck Converter using Novel Ramp Generation Technique
Asish Jaldu, Megha T S, Laqueta N, Harshitha G R, Rashmi Seethur PES UNIVERSITY |
| 9:55 |
Session PW3 -
PW3.4:
Modeling of Short and Aging Faults in TSVs at the Physical Level with Parametric Variation Analysis
Prosen Kirtonia1, Shelby Williams1, Prasanna Kawatker1, Kasem Khalil2, Magdy Bayoumi3 1University of Louisiana at Lafayette, 2University of Mississippi, 3U. of Louisiana |
| 10:00 |
Session PW3 -
PW3.5:
Energy-Aware DNN Task Scheduling with Dynamic Batching and Frequency Adjustment
Vasileios Pentsos1 and Spyros Tragoudas2 1Southern Illinois University of Carbondale, 2Southern Illinois University Carbondale |
| 10:05 |
Session PW3 -
PW3.6:
LUTAccel: Look-up-Table based Vector Systolic Accelerator on FPGAs
Aashish Kumar Tiwary1, Saketh Gajawada2, Jay Shah3, Nanditha Rao4 1International Institute of Information Technology, Bangalore, 2InternationalInstituteofInformationTechnologyBangalore, 3International Institute of Information Technology Bangalore, 4IBM |
| 10:10 |
Session PW3 -
PW3.7:
AI-Driven Power Gating for Enhanced Energy Efficiency in Superscalar Processors
Naman Kalra IIT Tirupati |
| 10:15 |
Session PW3 -
PW3.8:
RECminThrash : Recency and Eviction Count Based Cache Replacement Policy to Minimize Thrashing at the Last Level Caches
Chetan Kumar1 and Arijit Nath2 1Indian Institute of Information Technology, Guwahati, 2IIIT Guwahati |
| 10:20 |
Session PW3 -
PW3.9:
ColdStore: An STT sibling-cache architecture for energy-efficient intermittent computing systems
Rishabh Mahanta and Hemangee Kapoor Indian Institute of Technology Guwahati |
| 10:25 |
Session PW3 -
PW3.10:
Precision Unwound: Fine-Tuning Loop Unrolling for Energy-efficient FPGA-based PQC using HLS
Srijeet Guha1 and Andrea Guerrieri2 1Nvidia, 2EPFL and HES-SO |
|
Session 3A - Simulation and Analysis in VLSI Design
Chair: TBD, TBD Co-Chair: TBD, TBD |
| 10:45 |
Session 3A -
3A.1:
DAPP: Delay Aware Power Prediction
Sagar Satapathy and Dip Sankar Banerjee Indian Institute of Technology Jodhpur |
| 11:05 |
Session 3A -
3A.2:
Thermal Model Extraction at Chip Boundaries for Thermal Simulation of Chip in a System
Kai-Xiang Lin, Yu-Min Lee, Bo-Yi Tsai National Yang Ming Chiao Tung University |
| 11:25 |
Session 3A -
3A.3:
Analysis of VF-TLP ESD Measurements Using Machine Learning
Seyed Hossein Hosseini1, Mehrdad Nourani1, Theo Smedes2, Charvaka Duvvury3 1The University of Texas at Dallas, 2NXP Semiconductors, 3iT2 Technologies |
| 11:45 |
Session 3A -
3A.4:
Machine Learning-Based Pruning Algorithm of Partitioning Techniques for Circuit Simulation
Qian Chen, Xiaofeng Yang, Shengli Lu Southeast University |
|
Session 3B - Recent Trends in Cognitive Computing Hardware
Chair: Hongyu An, Michigan Technological University |
| 10:45 |
Session 3B -
3B.1:
Explainable AI-Guided Efficient Approximate DNN Generation for Multi-Pod Systolic Arrays
Ayesha Siddique1, Khurram Khalil1, Khaza Anuarul Hoque2 1University of Missouri-Columbia, 2University of Missouri |
| 11:05 |
Session 3B -
3B.2:
PhotoGAN: Generative Adversarial Neural Network Acceleration with Silicon Photonics
Tharini Suresh, Salma Afifi, Sudeep Pasricha Colorado State University |
| 11:25 |
Session 3B -
3B.3:
Keep All in Memory with Maxwell: a Near-SRAM Computing Architecture for Edge AI Applications
Gregoire Axel Eggermann1, Giovanni Ansaloni1, David Atienza2 1EPFL, 2École Polytechnique Fédérale de Lausanne (EPFL) |
| 11:45 |
Session 3B -
3B.4:
Efficient digital architecture of spiking encoders for neuromorphic accelerators
Ruizhe Li, Muhammad Farhan Azmine, Gauri Sharma, Yang Yi Virginia Tech |
| 12:05 |
Session 3B -
3B.5:
Region Masking to Accelerate Video Processing on Neuromorphic Hardware
Sreetama Sarkar1, Sumit Bam Shrestha2, Yue Che1, Leobardo E Campos Macias2, Gourav Datta3, Peter Beerel4 1University of Southern California, 2Intel Labs, 3Case Western Reserve University, 4Univ. of Southern California |
|
Session 3C - Generative AI on Edge
Chair: Amey Kulkarni, NVIDIA Co-Chair: Bharat Prakash, Qualcomm |
|
Session 4A - VLSI Physical Design Methodologies
Chair: TBD, TBD Co-Chair: TBD, TBD |
| 14:10 |
Session 4A -
4A.1:
Obstacle-aware Synthesis of the Bus Topology Considering Wire Length Minimization
Meng Lian1, Yushen Zhang1, Mengchu Li1, Tsun-Ming Tseng1, Shejun Sun2, Ulf Schlichtmann1 1Technical University of Munich, 2Huawei Device Co., Ltd |
| 14:30 |
Session 4A -
4A.2:
A Comprehensive Approach to Characterizing VT Miscorrelation Derates for Physical Design and Timing Signoff
Pravin Chandran, Hitesh Sharma, Srinivas Bodapati Intel |
| 14:50 |
Session 4A -
4A.3:
Open-ALOE: An Analog Layout Automation Flow for the Open-Source Ecosystem
Yueting Li1, Xingyu Ni2, Sara Achour2, Boris Murmann3 1University of California, Berkeley, 2Stanford University, 3University of Hawaii, Mānoa |
| 15:10 |
Session 4A -
4A.4:
Improving Routability Prediction via NAS Using a Smooth One-shot Augmented Predictor
Arjun Sridhar, Chen-Chia Chang, Junyao Zhang, Yiran Chen Duke university |
|
Session 4B - Security Evaluation in Complex Designs
Chair: TBD, TBD |
| 14:10 |
Session 4B -
4B.1:
Genetic Algorithm-Assisted Golden-Free Standard Cell Library Extraction from SEM Images
Mengdi Zhu, Ronald Wilson, Reiner N. Dizon-Paradis, Olivia P. Dizon-Paradis, Domenic Forte, Damon L. Woodard University of Florida |
| 14:30 |
Session 4B -
4B.2:
A Framework for PCB Design File Reconstruction from X-ray CT Annotations
Carson Sobolewski, David Koblah, Domenic Forte University of Florida |
| 14:50 |
Session 4B -
4B.3:
i-Know What You Do: Privacy Evaluation of Apple Smartphones with Remote Acoustic Side-Channels
Oswa Amro, Sanapala Jaswanth, Sai Dishanth Banoth, Urbi Chatterjee Indian Institute of Technology Kanpur |
| 15:10 |
Session 4B -
4B.4:
ML-based Real-Time URL Inspection with Hardware Acceleration for Enhanced Web Security
Majid Nezarat1, Erfan Khedersolh1, Hadi Shahriar Shahhosseini1, Amin Rezaei2 1Iran University of Science and Technology, 2California State University, Long Beach |
| 15:30 |
Session 4B -
4B.5:
MATTER: MULTI-STAGE ADAPTIVE THERMAL TROJAN FOR EFFICIENCY & RESILIENCE DEGRADATION
Mehdi Elahi1, Mohamed R.Elshamy2, Abdel-Hameed A. Badawy2, Mahdi Fazeli3, Ahamd Patooghy1 1North Carolina A&T state University, 2New Mexico state university, 3Halmstad University |
|
Session 4C - Hardware Techniques in Quantum Computing Security
Chair: Yuntao Liu, Lehigh University |
|
Session 5A - Memristive and Charge-Trap Devices for Next-Gen Computing
Chair: TBD, TBD Co-Chair: TBD, TBD |
| 9:00 |
Session 5A -
5A.1:
Behavioral Model of Charge-Trap Transistors for Neuromorphic Systems
Ataollah Saeed Monir1, Navid Rezazadeh2, John Gosson2, Boris Vaisband3 1McGill university, 2Blumind, 3University of California, Irvine |
| 9:20 |
Session 5A -
5A.2:
All-Optical Reconfigurable Activation Function based on Saturable Absorption
Oceane Destras1, Felipe Gohring de Magalhaes2, Sébastien Le Beux3, Gabriela Nicolescu2 1Polytechnique Montreal, 2Polytechnique Montréal, 3Concordia University |
| 9:40 |
Session 5A -
5A.3:
Formal Verification of Error Bounds for Resistive-Switching-based Multilevel Matrix-Vector Multipliers
Kemal Çağlar Coşkun1, Chandan Kumar Jha2, Muhammad Hassan3, Rolf Drechsler4 1Institute of Computer Science, University of Bremen, 2University of Bremen, 3Institute of Computer Science, University of Bremen / DFKI, 4University of Bremen/DFKI |
| 10:00 |
Session 5A -
5A.4:
Robust and Efficient NAND-like TST-MRAM with Parallel Write/Read Operations and Reconfigurable PUF Mode
Songhan Zhang, Xianzeng Guo, Yaling Wang, Chao Wang, Bi Wang, Zhaohao Wang Beihang University |
| 10:20 |
Session 5A -
5A.5:
A Novel Full Adder Design Using Hybrid Memristor Ratioed Logic
Hussein Fadlallah1, Rouwaida Kanj2, Basma Hajri3 1American University of Beirut, 2Synopsys, 3Qualcomm |
|
Session 5B - AI-Driven Embedded Computing and Power-Aware System Design
Chair: TBD, TBD |
| 9:00 |
Session 5B -
5B.1:
V-SYNC-Aware GPU DVFS Governor for Efficient Game Application Execution on Mobile Devices
En-Ming Huang1, Lono Kao2, Dino Lu2, Chun-Yi Lee3 1Google/National Taiwan University, 2Google, 3Department of Computer Science and Information Engineering, National Taiwan University |
| 9:20 |
Session 5B -
5B.2:
Energy-Efficient QoS-Aware Scheduling for S-NUCA Many-Cores
Sudam M Wasala1, Jurre Wolff1, Yixian Shen1, Anuj Pathania1, Clemens Grelck2, Andy Pimentel1 1University of Amsterdam, 2Friedrich Schiller University Jena |
| 9:40 |
Session 5B -
5B.3:
Deep Neural Network Inference Partitioning in Embedded Hybrid Analog-Digital Systems
Fabian Kreß1, Julian Hoefer2, Qiushi Lin3, Patrick Schmidt2, Zhenhua Zhu3, Yu Zhu3, Tanja Harbaum4, Yu Wang3, Juergen Becker1 1Karlsruhe Institute of Technology - ITIV, 2Karlsruhe Institute of Technology, 3Tsinghua University, 4KIT |
| 10:00 |
Session 5B -
5B.4:
Real-time Thermal Map Characterization and Analysis for Commercial GPUs with AI Workloads
Jincong Lu1, Sachin Sachdeva1, Yuxuan Lin2, Sheldon Tan3 1University of California, Riverside, 2The Overlake School, 3University of California at Riverside |
| 10:20 |
Session 5B -
5B.5:
IMU-based Motion Trajectory Reconstruction and Recognition with Dynamic Calibration on Embedded System Platform
Kai-Po Hsu1, Tsung-Han Lai1, Yi-Ting Li1, Wuqian Tang1, Yun-Ju Lee2, Yung-Chih Chen3, Wen-Hsin Chiu1, Chun-Yao Wang1 1National Tsing Hua University, 2National Tsing-Hua University, 3National Taiwan University of Science and Technology |
|
Session 5C - Design Innovation and Accelaration in the Nanometer Era
Chair: TBD, TBD |
| 9:20 |
Session 5C -
5C.2:
A Time-Borrowing Method for High-Performance Bundled-Data Asynchronous Circuits
Bohan Wang1, Zeyang Xu1, Lingfeng Zhou2, Huiyao Wang1, Jinghai Wang1, Zhiyi Yu1, Shanlin Xiao1 1School of Microelectronics Science and Technology, Sun Yat sen University, 2Sun Yat-Sen University |
| 9:40 |
Session 5C -
5C.3:
Machine Learning Assisted Magnetic-core Coupled Inductor Design for Interleaved Buck Converter
Maliha Elma, Navya Goli, Umamaheswara Tida North Dakota State University |
| 10:00 |
Session 5C -
5C.4:
Piecewise-Linear Approximation of Self-Attention and Its Accuracy-Aware Training for Area-Efficient Vision Transformer Inference Accelerator
Teppei Kawamura1, Yutaka Masuda2, Tohru Ishihara2 1Nagoya Univercity, 2Nagoya University |
| 10:20 |
Session 5C -
5C.5:
A Modified RC and Delay based ESD Clamp Circuit with False-trigger Immunity during normal supply operation.
Naresh Kumar, Divya Agarwal, Rajesh Narwal STMicroelectronic |
|
Session 6A - Advances in Quantum Computing: Security, Optimization, and AI Integration
Chair: TBD, TBD Co-Chair: TBD, TBD |
| 10:45 |
Session 6A -
6A.1:
Watermarking of Quantum Circuits
Rupshali Roy and Swaroop Ghosh Pennsylvania State University |
| 11:05 |
Session 6A -
6A.2:
Optimizing Quantum Embedding using Genetic Algorithm for QML Applications
Koustubh Phalak1, Archisman Ghosh2, Swaroop Ghosh1 1Pennsylvania State University, 2The Pennsylvania State University |
| 11:25 |
Session 6A -
6A.3:
Quantum Prometheus: Defying Overhead with Recycled Ancillas in Quantum Error Correction
Avimita Chatterjee1, Archisman Ghosh2, Swaroop Ghosh1 1Pennsylvania State University, 2The Pennsylvania State University |
| 11:45 |
Session 6A -
6A.4:
AI-driven Reverse Engineering of QML Models
Archisman Ghosh1 and Swaroop Ghosh2 1The Pennsylvania State University, 2Pennsylvania State University |
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Session 6B - Advanced Signal Processing and AI Acceleration
Chair: TBD, TBD |
| 11:05 |
Session 6B -
6B.2:
A Generalized Hardware-Efficient Gabor Wavelet Architecture for Medical Image Processing
Priyanka Agarwal1, Pruthvi Parate2, Madhav Rao3 1IIIT Bangalore, 2International Institute of Information Technology Bangalore, 3International Institute of Information Technology-Bangalore |
| 11:25 |
Session 6B -
6B.3:
Notch filter based Readout Interface for Hall-effect sensors for DC and High-Frequency Currents
Ayesha Hassan, Aireen Amir Jalal, Asma Mahar, Alan Mantooth University of Arkansas |
| 11:45 |
Session 6B -
6B.4:
Design and Implementation of a 1.8V OVT Driver with SCR-Based ESD Protection in 4nm FinFET Technology
Diogo pataco, Ehsanollah Fallah, Bart Keppens Sofics |
|
Session 6C - Hardware Techniques in Quantum Computing Security
Chair: Yuntao Liu, Lehigh University |
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Session 7B - Optimizing Memory, Power, and Computation for Next-Gen Systems
Chair: TBD, TBD |
| 12:55 |
Session 7B -
7B.1:
Exploiting The Presence of Abundant Zero Data to Improve NVM Lifespan
Arijit Nath and Harsh Raj IIIT Guwahati |
| 13:15 |
Session 7B -
7B.2:
Battery State of Health Estimation Using LLM Framework
Aybars Yunusoglu1, Dexter Le2, Karn Tiwari3, Murat Isik4, I. Can Dikmen5 1Purdue University, 2Drexel University, 3Indian Institute of Science, Bangalore, 4Stanford University, 5Temsa Research & Development Center |
| 13:35 |
Session 7B -
7B.3:
SPEED: Scalable and Predictable EnhancEments for Data Handling in Autonomous Systems
Dongjoo Seo1, Changhoon Sung2, Junseok Park3, Ping-Xiang Chen1, Bryan Donyanavard2, Nikil Dutt1 1University of California, Irvine, 2San Diego State University, 3Kookmin University |
| 13:55 |
Session 7B -
7B.4:
An FPGA-based Emulation Process for Dynamic Quantum Circuits
Yicheng Song and Zeljko Zilic McGill University |
| 14:15 |
Session 7B -
7B.5:
Sharp-Edge: A Robust Edge Computing Solution through Performance Monitoring Using Tiny Machine Learning
Mehdi Amininasab1, Mahdi Fazeli2, Ahmad Patooghy3 1Independent Scholar, 2Halmstad University, 3North Carolina A&T State University |
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Session 7C - Security or IoT??
Chair: TBD, TBD |