This paper presents a AI based static algorithm for fine-grained power gating of functional units in a superscalar processor. The proposed reinforcement learning agent leverages a multi-layer perceptron (MLP) neural network model as a policy to predict and control the power states of different functional units across four modes: On, Sleep-on, Sleep-off, and Off. By analyzing features from each basic block in the control flow graph and execution profile, the MLP model statically selects optimal power states for each unit. Traditional power gating techniques often struggle with trade-offs between minimizing performance loss (wake-up latency) and reducing power consumption, necessitating a reevaluation of power management strategies. Next-generation complex SoC designs at < 7nm technology nodes require a finer granularity approach to effectively manage power states. Our AI-based algorithm provides an optimized trade-off between power efficiency and performance by enabling power gating across multiple power states and selecting the power state that has the effectively least energy-delay product. Additionally, we propose an architectural circuit design for power gating multiple FU's within a superscalar processor, enabling efficient state transitions. Preliminary experimental results show that the proposed AI-based method achieves 10-20% energy savings while improving performance by 1.5% compared to traditional power gating algorithms.