The bus topology, crucial in electronics for multi-device communication, faces challenges with an increasing number of devices and application-specific physical constraints. This work mathematically models bus topological features and obstacle-aware routing constraints in the rectilinear and octilinear routing planes to synthesize the bus topology with minimized total wire length. We implement our rectilinear and octilinear synthesis methods by constructing mixed-integer-linear programming (MILP) models and investigate their performance using eleven commercial inter-integrated circuit (I2C) buses on a smartphone motherboard. Experimental results confirm that our methods can efficiently synthesize bus topologies with significantly shorter wire lengths, up to 24.3%, compared to two baseline methods.