We present a runtime reconfigurable Field Programmable Crossbar Array (FPCA) architecture designed to enable high-accuracy multiplication and division alongside high throughput ML operations. Our innovative in-memory compute-based multiplier and divider designs employing novel partial product reduction techniques support expandable multi-precision floating-point operations. Leveraging advanced interface and peripheral design techniques, our error-resilient FPCA achieves 0% error for in-memory digital operations, demonstrating remarkable robustness and reliability despite device and crossbar irregularities. Additionally, our architecture enhances neural network training throughput by 63.8x and improves power efficiency by 5.18x compared to state-of-the-art memristor-based accelerators. This work paves the way for future developments in high-performance, error-resistant in-memory computing solutions.