Electrostatic discharge (ESD) is a well-known problem in integrated circuits that affects the reliability, yield, and cost of the IC. It is important to design ESD protection circuits that can protect the integrated circuits from ESD stress and not affect the functionality of the system. In this work, a modified power-rail ESD clamp circuit which have optimized power on disabled logic, is proposed and implemented in 28-nm CMOS process. Simulation results show that the proposed disabled logic does not impact the functionality of the ESD power clamp during ESD event and ensure that ESD power clamp not trigger due to overshoot and undershoot on the supply line during normal supply operation.