Ensuring memory data integrity is essential for the reliable operation of modern computing infrastructures. As data processing demands surge, driven by advancements in fields such as artificial intelligence, DDR memory speeds have escalated rapidly. Originally specified to reach a maximum speed of 6400 MT/s, DDR5 is now projected to exceed 9600 MT/s to meet the increased requirements for memory bandwidth. With data rates currently approaching 8000 MT/s, verifying that both memory controllers and DRAM chips adhere to JEDEC specifications is becoming increasingly crucial to maintaining performance and reliability. For a DDR5 RDIMM operating at 8000 MT/s, clock, DQ, and CA signals run at 4 GHz, requiring precise handling in a dense layout of hundreds of high-frequency, single-ended traces. Probing such a high volume of multi-gigahertz signals simultaneously presents significant challenges for traditional test equipment. Currently, only a few protocol analyzers on the market are capable of this level of probing, and all face bandwidth limitations. This article introduces a novel technique that leverages a standard DDR5 Registering Clock Driver (RCD) as a probing front end, enabling more effective analysis of the DDR5 RDIMM bus. This technique extends the capabilities of bandwidth-limited protocol analyzers to probe DDR5 buses operating well beyond their rated bandwidth.