Computing-in-Memory (CIM) technology, particularly Resistive Random-Access Memory (RRAM) crossbar architectures, has shown promise in addressing the limitations of traditional architectures by integrating computation directly within memory arrays. However, a critical challenge remains the presence of unused word lines in the crossbar array, which leads to resource redundancy and inefficiencies caused by non-uniform data distribution, resulting in wasted energy, increased latency, and underutilized computational capacity. In this paper, we propose a novel circuit design that mitigates the adverse effects of redundancy in unused rows by introducing the alternating current (AC) signal into the system, combined with a bitline terminal filter that effectively separates new computations from interference caused by previous operations. Experimental results demonstrate that the inference accuracy adopted by our design maintains around 90% within 1% variations in LeNet5, VGG8, and ResNet. Moreover, the simulation results show that our design increases throughput up to 1.74 times compared to fully AC-controlled (FAC) designs.