The significance of utilizing chiplets and 3D ICs is rapidly increasing due to the slowing of Moore's Law and its associated advantages. Advanced packaging of chiplets and interconnects in 3D ICs is crucial for enhancing performance. Hence, Through-Silicon Vias (TSVs) serve as prominent vertical conduits to ensure efficient chip-to-chip communication. The primary objective of this work is to model TSV faults at the material level to observe electromagnetic (EM) performance deviations alongside other parametric analyses. We employ Ansys High-Frequency Structure Simulator (HFSS) to design the TSV at the physical level. The reflection coefficient is measured over a 0.1-30 GHz frequency band to observe −15 dB bandwidth for a wide range of lengths (30-200 μm), radius (4-50 μm), and dielectric thickness (0.2-1.5 μm), considering distinct densities. Furthermore, a crack of 5-15 μm is introduced in the dielectric layer to implement a short fault, and copper conductance is reduced by 5-30% for different stages of aging faults to evaluate anomalies. Finally, multiple TSVs are incorporated into the design to assess near-end and far-end cross-talk at 15 and 30 μm pitch. Therefore, before developing an equivalent R-L-C circuit for fault detection, it is essential to investigate functionality and faults at the physical level for a more comprehensive understanding.