The Elliptic Curve Digital Signature Algorithm (ECDSA) is a cryptographic method superior to the existing Digital Signature Algorithm (DSA). ECDSA utilizes an elliptic curve formulation for achieving tighter security and efficiency, making it well-suited for resource-constrained environments. This work presents a study of the ECDSA architecture, including the design and implementation of optimized GF(2163) Karatsuba mul- tipliers for signature generation and verification. The design was synthesized on a Kintex Ultrascale FPGA board and on silicon using the gpdk-45 nm technology library. We investigated the complete signature generation and verification architecture with non-homogeneous and composite Karatsuba multiplier variants and compared them with state-of-the-art (SOTA) multipliers over hardware metrics. Furthermore, we extracted and compared the results for the multiplier implementation alone, showing superior performance over the SOTA. The M-term Non-Homogeneous Karatsuba Multiplier (MNHKA), integrated into the ECDSA architecture, demonstrated the most hardware-efficient design on both FPGA and silicon, achieving substantial LUT savings of 50.42% and 37.50%, latency improvements of 52.29% and 43.86%, and throughput benefits of 16.66% and 43.86% for sig- nature generation and verification accelerator units, respectively. Additionally, footprint gains on silicon were 56.63% for signature generation and 45.99% for verification units compared to SOTA designs. These efficient variants of polynomial multipliers are found to be apt for ECDSA hardware accelerators over other existing forms of designs and is therefore, expected to enhance hardware security, reliability, and performance. All the hardware design files are made freely available for further usage to the designers and researchers community.