A True Random Number Generator (TRNG) is a crucial component in cryptographic hardware and security protocols, as the quality of generated random bits directly impacts the strength of encryption and overall security. High-quality random bits are characterized by high bit rate and resistance to decryption attempts. This paper introduces a novel resource-efficient TRNG design utilizing the carry chain available on the Zynq 7000 development board to construct an XORed carry chain latch-based ring oscillator with LUT-ring oscillators as latch-enable signals. The design incorporates LUT configured as ring oscillators with prime stages and an up/down counter-based correction scheme to refine the generated bits into true random bits with high entropy. The proposed TRNG design achieves throughput of 464 Mbps at a frequency of 464 Mhz. The generated random bits were using the NIST statistical test suites SP800-22 for randomness assessment and SP800-90B for entropy evaluation, successfully passing both with minimum byte entropy of 7.855885 and passing the AIS31 tests, standard for evaluating the random bits for cryptographic application. Compared to the best state-of-the-art (SOTA) designs, the proposed architecture demonstrates a 1.54x increase in throughput and frequency, with 4.29x less resource utilization and a 7.6x improvement in the figure of merit (FOM).