Charge trap transistors serve as non-volatile analog memory devices within standard CMOS technology. The effective incorporation of CTTs into neuromorphic circuits has proven, however, to be a demanding task, primarily due to the lack of design tools that can accurately model the charge trapping effect, impeding efficient design and simulation. A simplified model capturing the charge-trapping behavior in CMOS devices fabricated in GF 22 nm FDSOI technology with high-k dielectric silicon-on-insulator, is proposed and experimentally verified in this work. The model is based on a linear correlation that is identified between the shift in threshold voltage ∆Vt (that occurs after programming the device) and the drain voltage applied to the device, within the range of relevant voltages. The proposed analytical model exhibits an average deviation of 3 mV from ∆Vt with a standard variation of 3.6 mV as compared to experimentally obtained data. The model has been integrated within standard design tools using Verilog-A, enabling the simulation of CTT-based neuromorphic circuits.