With the ever-increasing utilization of artificial intelligence in everyday life as well as the preciousness of well-trained models, the security of hardware accelerators supporting DNNs has become crucial. As a promising solution to prevent hardware IP theft, eFPGA redaction has emerged by selectively concealing critical components of the design and enabling authorized users to restore functionality post-fabrication by inserting the correct bitstream. In this paper, for the first time, we delve into redacting DNN accelerators via eFPGAs from specification to physical design implementation. In particular, we investigate the selection of critical DNN modules for redaction using regular and fracturable look-up tables and perform synthesis, timing verification, and place & route on redacted DNN accelerators. Furthermore, we evaluate the overhead of employing eFPGAs into DNN accelerators in terms of power, area, and delay, finding it reasonable given the security gain.