This paper presents the design and optimization of NAND-like toggle spin torques magnetic random-access memory (TST-MRAM) to meet the stringent requirements of high-density cache applications in terms of speed, power consumption, and reliability. The proposed design tackles the reliability challenges associated with parallel write operations by decoupling the spin-orbit torque (SOT) current from the spin-transfer torque (STT) current, thereby simplifying voltage supply management and enhancing control precision. A dual-end write method is introduced to effectively minimize SOT current interference during the STT phase, resulting in improved write reliability and a reduction in the maximum write error rate from 20.5% to 0. To further enhance performance, a dual-end read method is employed, mitigating potential offsets caused by the states of neighboring devices. The proposed approach significantly improves read reliability, reducing the maximum read error rate from 3.1E-2 to 5.5E-7. Additionally, the NAND-like TST-MRAM is applied to physical unclonable functions (PUFs), exploiting its parallel random number generation capabilities to lower the average power consumption during PUF reconfiguration. Compared to conventional TST-MRAM design, the proposed approach can achieve 37.5% reduction in average bit-cell area and approximately 70% decrease in PUF reconfiguration power consumption.