Today's layout flow for analog integrated circuits is largely manual and has seen limited adoption of automation tools due to their required setup time, programming overhead and typically steep learning curve for the designer. The work described in this paper attempts to address this problem by repurposing tools that are already familiar to circuit designers and available within the open-source ecosystem, providing exposure to a large number of potential users and community-driven improvements. Our approach is based on the ALOE flow, which employs a digital place-and-route (PnR) tool in conjunction with genetic algorithms to produce analog layouts with acceptable performance in an iterative manner. Except for the PnR core, the current version of our flow primarily relies on open-source tools like Xschem, Ngspice, Netgen, Magic and Mflowgen. To validate the approach, we auto-generate layouts of a bandgap reference designed in SkyWater's 130-nm open-source CMOS technology. Within a runtime of approximately 30 minutes, our flow produces 560 candidate layouts that gradually evolve and improve through the genetic algorithm. The bandgap design generated by our flow is fabricated in SkyWater's 130-nm CMOS technology, tested, and demonstrates a voltage error of 7.8 mV with 100x speed-up compared to the manual layout.