The reduction of die size has been a primary goal in systems-on-chip (SoC) designs. While previous approaches focused on reducing congestion of the chip as a whole, there has been little effort to specifically alleviate congestion in the top channel. In channel-based hierarchical non-IO limited SoC designs, inserting feedthroughs can be a crucial step during the floorplan stage to enhance routing resource utilization, alleviate congestion in the top channels, and ultimately save die area. Traditional feedthrough insertion approaches are usually carried out manually or managed in a flattened design. However, it is challenging to handle the large number of connections at the top, the high dependency on RTL, the integration of new feedthrough ports at the subchip level, and the verification of logical equivalence. We propose a method to address these challenges by employing a novel feedthrough insertion approach.