High-Level Synthesis (HLS) is a valuable tool for designing hardware accelerators for Post-quantum Cryptography (PQCs). However, while HLS can efficiently map high-level code to hardware, the quality of the synthesized hardware in terms of latency, power, and area is sensitive to various design parameters and configurations, such as loop unrolling, pipelining, and dataflow optimizations. In this work, we explore the effects of loop unrolling on the execution time and the energy efficiency of the final PQC. We demonstrate that, despite initial expectations, loop unrolling could worsen the performance.