Network on Chip (NoC) serves as a scalable and cost-effective choice for communication between the cores in multicore or manycore systems. As the number of cores on an Integrated Circuit (IC) increases, so does the risk of defects during manufacturing of these multicore systems. This makes the manufacturing test procedures increasingly important. Finding an optimal test schedule from the large-scale system is extremely time-consuming and a complex optimization task. In this paper, we propose a Machine Learning (ML) framework (MAPIC) to enhance the mapping of test cores to the IO pairs in the network, aiming to generate an optimal test schedule for the NoC-based system. The experimental results indicate the effectiveness of the proposed framework as it outperforms a meta-heuristic-based optimization technique.