Chair: Sreejit Chakravarty, LSI Corporation
Co-Chair: Srivatsa Vasudevan, Synopsys Inc.

10:20AM
1A.1
Physical-Design-Friendly Hierarchical Logic Built-In Self-Test – A Case Study
Kelvin Nelson¹,  Jaga Shanmugavadivelu¹,  Jayanth Mekkoth¹,  Venkat Ghanta¹,  Jun Wu¹,  Fe Zhuang¹,  Hao-Jan Chao²,  Shianling Wu²,  Jie Rao²,  Lizhen Yu²,  Laung-Terng Wang^2
1Cisco Systems, ²SynTest Technologies, Inc.

10:40AM
1A.2
A Self-Testable SiGe LNA and Built-in-Self-Test Methodology for Multiple Performance Specifications of RF Amplifiers
Abhilash Goyal¹,  Madhavan Swaminathan²,  Abhijit Chatterjee²,  Duane Howard²,  John Cressler^2
1Oracle, Santa Clara, CA, USA, ²GaTech, Atlanta, USA

11:00AM
1A.3
Improved Path Clustering for Adaptive Path-Delay Testing
Tuck-Boon Chan and Andrew Kahng
UCSD

11:20AM
1A.4
TSV and DFT Cost Aware Circuit Partitioning for 3D-SOCs
Amit Kumar¹,  Sudhakar M. Reddy¹,  Irith Pomeranz²,  Bernd Becker^3
1Dept. of ECE, University of Iowa, Iowa City, USA, ²School of ECE, Purdue Univ, West Lafayette, USA, ³Dept of Computer Sci, Univ of Freiburg, Freiburg, Germany

11:40AM
1A.5
A Design-For-Test Apparatus for Measuring On-Chip Temperature with Fine Granularity
James Tandon,  Masahiro Sasaki,  Makoto Ikeda,  Kunihiro Asada
University of Tokyo

Chair: Payman Zarkesh-Ha, University of New Mexico
Co-Chair: Srinivas Bodapati, Intel

10:20AM
1B.1
Wearout-Aware Compiler-Directed Register Assignment for Embedded Systems
Fahad Ahmed¹,  Mohamed Sabry²,  David Atienza²,  Linda Milor^1
1Georgia Institute of Technology, ²Ecole Polytechnique Federale de Lausanne

10:40AM
1B.2
Process-Variation Aware Mapping of Real-Time Streaming Applications to MPSoCs for Improved Yield
Davit Mirzoyan¹,  Benny Akesson²,  Kees Goossens^2
1Delft University of Technology, ²Eindhoven University of Technology

11:00AM
1B.3
Single Fault Reliability Analysis in FPGA Implemented Circuits
Hadi Jahanirad¹,  Karim Mohammadi¹,  Pejman Attarsharghi^2
1College of Electrical Engineering, Iran University of Science and Technology, Tehran, Iran, ²Electronics Research Center, Sharif University of Technology, Tehran, Iran

11:20AM
1B.4
Low Complexity Cross Parity Codes for Multiple and Random Bit Error Correction.
Mahesh Poolakkaparambil¹,  Jimson Mathew¹,  Abusaleh Jabir²,  Saraju Mohanty^2
1Oxford Brookes University, ²University of North Texas

11:40AM
1B.5
Delay Insensitive Code-Based Timing and Soft Error-Resilient and Adaptive-Performance Logic
Bao Liu,  Xuemei Chen,  Fiona Teshome
University of Texas at San Antonio

Chair: Makram Mansour, Texas Instruments
Co-Chair: Jose Silva Matos, University of Porto

10:20AM
1C.1
Online Mapping of Embedded Applications on MPSoCs
Nasreddine Hireche and Samar Abdi
Concordia University

10:40AM
1C.2
A Particle Swarm Optimization Approach for Synthesizing Application-specific Hybrid Photonic Networks-on-Chip
Shirish Bahirat and Sudeep Pasricha
Department of Electrical and Computer Engineering, Colorado State University

11:00AM
1C.3
A Preliminary Study on System-level Impact of Persistent Main Memory
Taciano Perez¹,  Ney Laert Vilar Calazans²,  Cesar A. F. De Rose^2
1Hewlett Packard, ²PUCRS

11:20AM
1C.4
Optimal Microarchitectural Design Configuration Selection for Processor Hard- Error Reliability
Ying Zhang,  Lide Duan,  Bin Li,  Lu Peng
Louisiana State University

11:40AM
1C.5
Noc-based platform for embedded software design: An extension of the Hellfire Framework
Felipe Magalhães,  Oliver Longhi,  Sérgio Filho,  Alexandra Aguiar,  Fabiano Hessel
Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)

Chair: Tan Yan, Synopsys, Inc.
Co-Chair: Martin Wang, UIUC

1:30PM
2A.1
Thermal Via Structural Design in Three-Dimensional Integrated Circuits
Leslie Hwang,  Kevin Lin,  Martin Wong
University of Illinois

1:50PM
2A.2
Functional Test Pattern Generation for Maximizing Temperature in 3D IC Chip Stack
Sudarshan Srinivasan and Sandip Kundu
Umass Amherst

2:10PM
2A.3
Thermal analysis of 3D integrated circuits based on discontinous Galerkin finite element method
Amir Zjajo,  Nick van der Meijs,  Rene van Leuken
Delft University of Technology

2:30PM
2A.4
Full-chip Thermal Analysis of 3D ICs with Liquid Cooling by GPU-Accelerated GMRES Method
Xue-Xin Liu,  Zao Liu,  Sheldon X.-D. Tan,  Joseph Gordon
University of California, Riverside

2:50PM
2A.5
Leakage-Aware Performance-Driven TSV-Planning Based on Network flow Algorithm in 3D ICs
Kan Wang¹,  Sheqin Dong¹,  Yuchun Ma¹,  Goto Satoshi²,  Jason Cong^3
1Tsinghua University, ²Waseda University, ³UCLA

3:10PM
2A.6
A 3D IC Designs Partitioning Algorithm with Power Consideration
Ho-Lin Chang,  Hsiang-Cheng Lai,  Tsu-Yun Hsueh,  Wei-Kai Cheng,  Mely Chen Chi
Chung Yuan Christian University

Chair: Syed Alam, Everspin Technologies Inc.
Co-Chair: Dinesh Somasekhar, Global Foundries

1:30PM
2B.1
Embracing Local Variability to Enable a Robust High-Gain Positive-Feedback Amplifier: Design Methodology and Implementation
Kareem Ragab,  Ranjit Gharpurey,  Michael Orshansky
University of Texas at Austin

1:50PM
2B.2
An Ultra-Low Voltage Digitally Controlled Low-Dropout Regulator with Digital Background Calibration
Yongtae Kim and Peng Li
Texas A&M University

2:10PM
2B.3
Dynamically biased low power High performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process
Karthik Rajagopal
Texas Instruments

2:30PM
2B.4
Design of an Efficient NoC Architecture using Millimeter-Wave Wireless Links
Sujay Deb¹,  Kevin Chang¹,  Amlan Ganguly²,  Xinmin Yu¹,  Partha Pande¹,  Christof Teuscher³,  Deuk Heo¹,  Benjamin Belzer^1
1Washington State University, ²Rochester Institute of Technology, ³Portland State University

2:50PM
2B.5
A Novel Robust Signaling Scheme for High-Speed Low-Power Communication over Long Wires
Marshnil Dave,  Maryam Shojaei Baghini,  Dinesh Sharma
IIT-Bombay

3:10PM
2B.6
An Extended-Range Incremental CT Sigma Delta ADC with Optimized Digital Filter
Julian Garcia and Ana Rusu
KTH Royal Institute of Technology

Chair: Rajan Beera, Texas Instruments
Co-Chair: Valeriy Sukharev, Mentor Graphics

1:30PM
2C.1
Test Structure, Circuits and Extraction Methods to Determine the Radius of Influence of STI and Polysilicon Pattern Density
Albert H. Chang¹,  Kewei Zuo²,  Jean Wang²,  Douglas Yu²,  Duane Boning^1
1Massachusetts Institute of Technology, ²Taiwan Semiconductor Manufacturing Company, Ltd.

1:50PM
2C.2
Post-Placement Lithographic Hotspot Detection and Removal in One-Dimensional Gridded Designs
Jen-Yi Wuu¹,  Mark Simmons²,  Malgorzata Marek-Sadowska^1
1University of California, Santa Barbara, ²Mentor Graphics Corporation

2:10PM
2C.3
On Lithography Aware Metal-Fill Insertion
Vikram Suresh,  Priyamvada Vijayakumar,  Sandip Kundu
University of Massachusetts, Amherst

2:30PM
2C.4
Understanding, Modeling, and Detecting Pooling Hotspots in Copper CMP
Aaron Gower-Hall¹,  Tamba Gbondo-Tugbawa¹,  JenPin Weng¹,  Wei-tsu Tseng²,  Laertis Economikos²,  Toshiaki Yanagisawa²,  Pavan Bashaboina²,  Stephen Greco^2
1Cadence Design Systems, ²IBM Semiconductor Research and Development Center

2:50PM
2C.5
Methodology for Analysis of TSV Stress Induced Transistor Variation and Circuit Performance
Li Yu¹,  Wen-Yao Chang²,  Kewei Zuo²,  Jean Wang²,  Douglas Yu²,  Duane Boning^1
1Microsystems Technology Laboratories, Massachusetts Institute of Technology, ²Taiwan Semiconductor Manufacturing Company, Ltd.

3:10PM
2C.6
High Performance Electrical Driven Hotspot Detection Solution for Full Chip Design using a Novel Device Parameter Matching Technique
Rami Fathy¹,  Mohamed Al-Imam¹,  Abdelrahman ElMously¹,  Haitham Eissa¹,  Ahmed Arafa¹,  Mohab Anis^2
1Mentor Graphics, ²American University in Cairo

Chair: James Lei, Applied Harmonics Corporation
Co-Chair: Anand Iyer, AMD

3:50PM
3A.1
Fast Delay Estimation with Buffer Insertion for Through-Silicon-Via-Based 3D Interconnects
Young-Joon Lee and Sung Kyu Lim
Georgia Institute of Technology

4:10PM
3A.2
Functional Composition: A New Paradigm for Performing Logic Synthesis
Mayler Martins,  Renato Ribas,  Andre Reis
UFRGS

4:30PM
3A.3
A New Voltage Binning Technique for Yield Improvement Based on Graph Theory
Ruijing Shen,  Sheldon X.-D. Tan,  Xue-Xin Liu
University of California, Riverside

4:50PM
3A.4
A Complete Power Estimation Methodology for DSP Blocks in FPGAs
Hassan Hassan and Nizar Abdallah
Microsemi Corp.

5:10PM
3A.5
Process Variation Aware DRAM Design Using Block Based Adaptive Body Biasing Algorithm
Satyajit Desai,  Sanghamitra Roy,  Koushik Chakraborty
Utah State University

Chair: Paul Tong, Pericom Semiconductor
Co-Chair: Bao Liu, University of Texas

3:50PM
3B.1
Device- and System-Level Performance Modeling for Graphene P-N Junction Logic
Chenyun Pan and Azad Naeemi
Georgia Institute of Technology

4:10PM
3B.2
Quasi-Planar Tri-gate (QPT) Bulk CMOS Technology for Single-Port SRAM Application
Yasumasa Tsukamoto¹,  Makoto Yabuuchi¹,  Hidehiro Fujiwara¹,  Koji Nii¹,  Changhwan Shin²,  Tsu-Jae King Liu^3
1Renesas Electronics Corporation, ²University of Soeul, ³University of California at Berkeley

4:30PM
3B.3
A Body-Voltage-Sensing-Based Short Pulse Reading Circuit for Spin-Torque Transfer RAMs (STT-RAMs)
Fengbo Ren,  Henry Park,  Richard Dorrance,  Yuta Toriyama,  C.-K. Ken Yang,  Dejan Marković
Department of Electrical Engineering, University of California, Los Angeles, CA, USA

4:50PM
3B.4
Interconnect analysis in spin-torque devices: performance modeling, optimal repeater insertion, and circuit-size limits
Shaloo Rakheja and Azad Naeemi
Georgia Institute of Technology

5:10PM
3B.5
Analysis of Crosstalk Delay and Area for MWNT and Bundled SWNT in Global VLSI Interconnects
Manoj Kumar Majumder,  Nisarg D. Pandya,  Brajesh Kumar Kaushik,  Sanjeev Kumar Manhas
Department of Electronics and Computer Engineering, Indian Institute of Technology Roorlee

Chair: Rajesh Garg, Intel
Co-Chair: Riaz Naseer, Intel

3:50PM
3C.1
Robust Metastability-based TRNG Design in Nanometer CMOS with Sub-Vdd Pre-charge and Hybrid Self-calibration
Vikram Suresh and Wayne Burleson
University of Massachusetts, Amherst

4:10PM
3C.2
Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices
Takashi Sato,  Hiromitsu Awano,  Hirofumi Shimizu,  Hiroshi Tsutsui,  Hiroyuki Ochi
Kyoto Univ.

4:30PM
3C.3
Error Mitigation in Digital Logic using a Feedback Equalization with Schmitt Trigger (FEST) Circuit
Zafar Takhirov,  Bobak Nazer,  Ajay Joshi
Boston University

4:50PM
3C.4
The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter
Hu Xu¹,  Vasilis F. Pavlidis¹,  Wayne Burleson²,  Giovanni De Micheli^1
1EPFL, ²University of Massachusetts Amherst

5:10PM
3C.5
TDDB-Based Performance Variation of Combinational Logic in Deeply Scaled CMOS Technology
Haiqing Nan,  Li Li,  Ken Choi
Illinois Institute of Technology

Chair: Mark Budnik, Valpraiso University
Co-Chair: Keith Bowman, Intel

5:30PM
P.1
Critical Area Driven Dummy Fill Insertion to Improve Manufacturing Yield
Nishant Dhumane and Sandip Kundu
University of Massachusetts, Amherst

5:30PM
P.3
Impact of Transistor Aging Effects on Sense Amplifier Reliability in Nano-Scale CMOS
Roberto Menchaca and Hamid Mahmoodi
San Francisco State University

5:30PM
P.4
A Highly Reliable SEU Hardened Latch and High Performance SEU Hardened Flip-Flop
Riadul Islam
Concordia University

5:30PM
P.5
A Scalable Curve-fit Model of the Substrate Coupling Resistances for IC Design
Vijaya Kumar Gurugubelli and Shreepad Karmalkar
Indian Institute of Technology Madras

5:30PM
P.6
Efficient Reduction Techniques for Statistical Model Generation of Standard Cells
Sachin Shrivastava and Harindranath Parameswaran
Cadence Design Systems

5:30PM
P.7
Efficient Electro-Thermal Co-analysis on CPU+GPU Heterogeneous Architecture
Kun Huang,  Xu Yang,  Guoxing Zhao,  Zuying Luo
College of Information Science and Technology, Beijing Normal University

5:30PM
P.8
Dynamic Range Estimation for Systems with Control-flow Structures
Bin Wu
AMD

5:30PM
P.9
Comparison of Variations in MOSFET versus CNFET in Gigascale Integrated Systems
Ali Arabi M. Shahi,  Payman Zarkesh-Ha,  Mirza Elahi
University of New Mexico

5:30PM
P.10
Vertical Slit Field Effect Transistor in Ultra-Low Power Applications
Xiang Qiu¹,  Malgorzata Marek-Sadowska¹,  Wojciech Maly^2
1University of California, Santa Barbara, ²Carnegie Mellon University

5:30PM
P.11
Design and Optimization of Power Gating for DVFS Applications
Tong Xu and Peng Li
Texas A&M University

5:30PM
P.12
An Area Efficient On-Chip Hybrid Voltage Regulator
Selcuk Kose¹,  Sally Pinzon²,  Bruce McDermott²,  Simon Tam³,  Eby Friedman^1
1University of Rochester, ²Eastman Kodak, ³Intel Corporation

5:30PM
P.13
Device and electromagnetic co-simulation of TSV: substrate noise study and compact modeling of a TSV in a matrix.
Patrick Le Maitre,  Melanie Brocard,  Alexis Farcy,  Jean-Claude Marin
STMicroelectronics

5:30PM
P.14
A Case for 3D Stacked Analog Circuits in High-Speed Sensing Systems
Mohammad Abdel-Majeed,  Mike S.W. Chen,  Murali Annavaram
University of Southern California

5:30PM
P.15
A DyadicCluster method used for Nonlinear Placement
Wenchao Gao¹,  Qiang Zhou¹,  Xu Qian²,  Yici Cai^1
1Tsinghua University, Beijing, ²China University of Mining and Technology, Beijing

5:30PM
P.16
Clock Mesh Framework
Pinaki Chakrabarti¹,  Vikram Bhatt²,  Dwight Hill³,  Aiqun Cao^3
1Synopsys Inc., Bangalore, India, ²University of California, San Diego, CA, USA, ³Synopsys Inc., Mountain View, CA, USA

5:30PM
P.17
Placement Aware Clock Gate Cloning and Redistribution Methodology
Vishweshwara Ramamurthy,  Mahita Nagabhiru,  Venkatraman Ramakrishnan
Texas Instruments India

5:30PM
P.18
Impact of C-Elements in Asynchronous Circuits
Matheus Moreira,  Bruno Oliveira,  Fernando Moraes,  Ney Calazans
PUCRS

5:30PM
P.19
A Top-Down Design Methodology using Virtual Platforms for Concept Development
Mohit Shah¹,  Brian Mears²,  Chaitali Chakrabarti¹,  Andreas Spanias^1
1Arizona State University, ²Intel Corporation

5:30PM
P.20
Partitioning and Dynamic Mapping Evaluation for Energy Consumption Minimization on NoC-Based MPSoC
Eduardo Antunes,  Matheus Soares,  Alexandra Aguiar,  Sergio Johann F.,  Marcos Sartori,  Fabiano Hessel,  Cesar Marcon
PUCRS

Chair: Makoto Ikeda, University of Tokyo
Co-Chair: Martin Wang, UIUC

10:20AM
4A.1
Ordinary Kriging Metamodel-Assisted Ant Colony Algorithm for Fast Analog Design Optimization
Oghenekarho Okobiah,  Saraju Mohanty,  Elias Kougianos
University of North Texas

10:40AM
4A.2
CMOS Op-amp Circuit Synthesis with Geometric Programming Models for Layout-Dependent Effects
Yu Zhang,  Bo Liu,  Bo Yang,  Jing Li,  Shigetoshi Nakatake
The University of Kitakyushu

11:00AM
4A.3
DRC-Free High Density Layout Exploration with Layout Morphing and Patterning Quality Assessment, with Application to SRAM
Amith Singhee¹,  Emrah Acar¹,  Mohammad Younus²,  Rama Singh³,  Aditya Bansal^1
1IBM T J Watson Research Center, ²IBM Corporation, ³

11:20AM
4A.4
Hierarchical Power Network Synthesis for Multiple Power Domain Designs
Chieh-Jui Lee¹,  Sean Shih-Ying Liu¹,  Chuan-Chia Huang¹,  Hung-Ming Chen¹,  Chang-Tzu Lin²,  Chia-Hsin Lee^2
1National Chiao Tung University, ²Industrial Technology Research Institute

11:40AM
4A.5
Algorithmic Study on the Routing Reliability Problem
Qiang Ma,  Zigang Xiao,  Martin D. F. Wong
University of Illinois at Urbana-Champaign

Chair: Srinivas Bodapati, Intel
Co-Chair: Hamid Mahmoodi, SFSU

10:20AM
4B.1
A 40-nm 256-Kb 0.6-V Operation Half-Select Resilient 8T SRAM with Sequential Writing Technique Enabling 367-mV VDDmin Reduction
Masaharu Terada¹,  Shusuke Yoshimoto¹,  Shunsuke Okumura¹,  Toshikazu Suzuki²,  Shinji Miyano²,  Hiroshi Kawaguchi¹,  Masahiko Yosimoto^1
1Kobe University, ²Semiconductor Technology Academic Research Center (STARC)

10:40AM
4B.2
Process Variation Tolerant 9T SRAM Bitcell Design
G K Reddy and jawar singh
Jaypee University of Engineering & Technology

11:00AM
4B.3
History & Variation Trained Cache (HVT-Cache) A Process Variation Aware and Fine Grain voltage Scalable Cache with Active Access History Monitoring
Avesta Sasan¹,  Houman Homayoun²,  Kiarash Amiri³,  Ahmed Eltawil³,  Fadi Kurdahi^3
1Broadcom, ²University of California San Diego, ³University of California Irvine

11:20AM
4B.4
VAR-TX: A Variability-Aware SRAM Model for Predicting the Optimum Architecture to achieve Minimum Access-Time for Yield Enhancement in Nano-scaled CMOS
Jeren Samandari-Rad,  Matthew Guthaus,  Richard Hughey
University of California, Santa Cruz

11:40AM
4B.5
Bit Error Rate Estimation in SRAM Considering Temperature Fluctuation
Yuki Kagiyama,  Shunsuke Okumura,  Koji Yanagida,  Shusuke Yoshimoto,  Yohei Nakata,  Shintaro Izumi,  Hiroshi Kawaguchi,  Masahiko Yoshimoto
Kobe University

Chair: Kamesh Gadepally, Texas Instruments
Co-Chair: Lalitha Immaneni, Intel

10:20AM
4C.1
Invited Paper 4C.1
Keith Bowman
Intel

10:40AM
4C.2
Chip-Package Power Delivery Network Resonance Analysis and Co-design Using Time and Frequency Domain Analysis Techniques
Jonathan Watkins¹,  Jai Pollayil²,  Calvin Chow²,  Aveek Sarkar^2
1Maxim, ²Apache Design Inc

11:00AM
4C.3
Maintaining Power Integrity by Damping the Cavity-Mode Anti-Resonances’ Peaks on a Power Plane by Particle Swarm Optimization
Jai Narayan Tripathi¹,  Raj Kumar Nagpal²,  Nitin Kumar Chhabra³,  Rakesh Malik³,  Jayanta Mukherjee^1
1Department of EE, IIT Bombay., ²CEC, STMicroelectronics Pvt. Ltd, Greater Noida, INDIA, ³TRnD, STMicroelectronics Pvt. Ltd, Greater Noida, INDIA

11:20AM
4C.4
A Design Tradeoff Study with Monolithic 3D Integration
Chang Liu and Sung Kyu Lim
Georgia Institute of Technology

11:40AM
4C.5
Cost-minimized Double Die DRAM Packaging for Ultra-High Performance DDR3 and DDR4 Multi-Rank Server DIMMs
Richard Crisp¹,  Bill Gervasi²,  Wael Zohni¹,  Bel Haba^3
1Invensas Corp, ²Discobolus Designs, ³Tessera Inc.

Chair: Masahiro Fujita, University of Tokyo
Co-Chair: Anand Iyer, AMD

1:30PM
5A.1
Speed-path Analysis for Multi-path Failed Latches with Random Variation
Tsutomu Ishida¹,  Izumi Nitta¹,  Katsumi Homma¹,  Yuzi Kanazawa¹,  Hiroaki Komatsu^2
1Fujitsu Labs. Ltd., ²Fujitsu Ltd.

1:50PM
5A.2
HiSIM-RP: A Reverse-Profiling Based 1st Principle Compact MOSFET Model and Its Application to Variability Analysis of 90nm and 40nm CMOS
Hironori Sakamoto¹,  Shigetaka Kumashiro¹,  Shigeo Sato²,  Naoki Wakita³,  Tohru Mogami^4
1Renesas Electronics Corp., ²Fujitsu Semiconductor Ltd., ³Toshiba Corp., ⁴NEC Corp.

2:10PM
5A.3
An Accurate Current Source Model for CMOS Based Combinational Logic Cell
Baljit Kaur,  Sandeep Vundavalli,  Sanjeev Kumar Manhas,  Sudeb Dasgupta,  Anand Bulusu
Indian Institute of Technology, Roorkee

2:30PM
5A.4
Efficient Approaches to Overcome Non-Convexity Issues in Analog Design Automation
Supriyo Maji and Pradip Mandal
IIT Kharagpur

2:50PM
5A.5
Optimization of Importance Sampling Monte Carlo using Consecutive Mean-shift Method and its Application to SRAM Dynamic Stability Analysis
Takeshi Kida,  Yasumasa Tsukamoto,  Yuji Kihara
Renesas Electronics Corporation

3:10PM
5A.6
Metamodel-Assisted Ultra-Fast Memetic Optimization of a PLL for WiMax and MMDS Applications
Oleg Garitselov,  Saraju Mohanty,  Elias Kougianos,  Oghenekarho Okobiah
University of North Texas

Chair: Cheng Zhuo, Intel
Co-Chair: Mark Budnik, Valpraiso University

1:30PM
5B.1
24% Power Reduction by Post-Fabrication Dual Supply Voltage Control of 64 Voltage Domains in VDDmin Limited Ultra Low Voltage Logic Circuits
Tadashi Yasufuku¹,  Koji Hirairi²,  Yu Pu¹,  Yun Fei Zheng¹,  Ryo Takahashi¹,  Masato Sasaki¹,  Hiroshi Fuketa¹,  Atsushi Muramatsu²,  Masahiro Nomura²,  Hirofumi Shinohara²,  Makoto Takamiya¹,  Takayasu Sakurai^1
1University of Tokyo, ²Semiconductor Technology Academic Research Center

1:50PM
5B.2
Enhancing Efficiency and Robustness of a Photovoltaic Power System under Partial Shading
Yanzhi Wang¹,  Xue Lin¹,  Younghyun Kim²,  Naehyuck Chang²,  Massoud Pedram^1
1University of Southern California, ²Seoul National University

2:10PM
5B.3
Comparison between power gating and DVFS from the view point of energy efficiency
Atsuki Inoue
Fujitsu Lab. Ltd.

2:30PM
5B.4
Design of Low-Power, Scalable-Throughput Systems at Near/Sub Threshold Voltage
Meeta Srivastav,  Michael Henry,  Leyla Nazhandali
Virginia Tech University

2:50PM
5B.5
Analysis and Evaluation of Greedy Thread Swapping Based Dynamic Power Management for MPSoC Platforms
Chirag Ravishankar¹,  Sundaram Ananthanaryanan²,  Siddharth Garg¹,  Andrew Kennings^1
1University of Waterloo, ²University of Waterloo/Anna University

3:10PM
5B.6
Efficient Leakage Power Saving by Sleep Depth Controlling for Multi-mode Power Gating
Seidai Takeda¹,  Shinobu Miwa¹,  Kimiyoshi Usami²,  Hiroshi Nakamura^1
1The University of Tokyo, ²Shibaura Institute of Technology

Chair: Shubhankar Basu, Global Foundries
Co-Chair: Saraju Mohanty, University of North Texas

1:30PM
5C.1
DDRO: A Novel Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators
Tuck-Boon Chan¹,  Puneet Gupta²,  Andrew Kahng¹,  LiangZhen Lai^2
1UCSD, ²UCLA

1:50PM
5C.2
An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design
Samatha Gummalla,  Anupama R Subramaniam,  Chaitali Chakrabarti,  Yu (kevin) Cao
Arizona State University

2:10PM
5C.3
Process Mismatch Analysis based on Reduced-Order Models
Mustafa B Yelten,  Paul D Franzon,  Michael B Steer
North Carolina State University

2:30PM
5C.4
Transistor Channel Decomposition for Structured Analog Layout, Manufacturability and Low-power Applications
Qing Dong,  Bo Yang,  Gong Chen,  Jing Li,  Shigetoshi Nakatake
The University of Kitakyushu, Japan

2:50PM
5C.5
Theory of Redundancy for Logic Circuits to Maximize Yield/Area
Mohammad Mirza-Aghatabar,  Melvin A. Breuer,  Sandeep K. Gupta,  Shahin Nazarian
University of Southern California

3:10PM
5C.6
A Novel Sample Reuse Methodology for Fast Statistical Simulations with Applications to Manufacturing Variability
Rouwaida Kanj¹ and Rajiv Joshi^2
1American University of Beirut - on IBM Leave, ²IBM

Chair: Srivatsa Vasudevan, Synopsys Inc.
Co-Chair: Sreejit Chakravarty, LSI Corporation

3:50PM
6A.1
Monitoring and Timing Prediction in Early Analyzing and Checking Performance of Interconnection Networks at ESL
Mao-Yin Wang and Jen-Chieh Yeh
Information & Communications Research Laboratories, Industrial Technology Research Institute

4:10PM
6A.2
Automated Correction of Design Errors by Edge Redirection on High-Level Decision Diagrams
Anton Karputkin,  Raimund Ubar,  Mati Tombak,  Jaan Raik
Tallinn University of Technology

4:30PM
6A.3
Assertion Clustering for Compacted Test Sequence Generation
Jason Tong¹,  Marc Boulé²,  Dr. Zeljko Zilic^1
1McGill University, ²École de Technologie Supérieure

4:50PM
6A.4
Transaction-Based Post-Silicon Debug of Many-Core System-on-Chips
Amir Masoud Gharehbaghi and Masahiro Fujita
University of Tokyo

5:10PM
6A.5
An Enhanced Debug-Aware Network Interface for Network-on-Chip
M. H. Neishaburi and Zeljko Zilic
McGill University

Chair: Paul Tong, Pericom Semiconductor
Co-Chair: Bao Liu, University of Texas

3:50PM
6B.1
Process Induced Mechanical Stress Aware Poly-Pitch Optimization for Enhanced Circuit Performance
Naushad Alam,  Sudeb Dasgupta,  Bulusu Anand
Indian Institute of Technology Roorkee, India

4:10PM
6B.2
Design Issues and Insights of Multi-Fin Bulk Silicon FinFETs
Hsun Li and Meng-Hsueh Chiang
National Ilan University

4:30PM
6B.3
Self-Heating Effects in Gate-all-around Silicon Nanowire MOSFETs: Modeling and Analysis
Xin Huang,  Tianwei Zhang,  Runsheng Wang,  Changze Liu,  Yuchao Liu,  Ru Huang
Institute of Microelectronics, Peking University

4:50PM
6B.4
Comparison of Electrical, Optical and Plasmonic On-Chip Interconnects Based on Delay and Energy Considerations
Shaloo Rakheja and Vachan Kumar
Georgia Institute of Technology

5:10PM
6B.5
Design Quality Tradeoff Studies for 3D ICs Built with Nano-scale TSVs and Devices
Kaiyuan Yang¹,  Dae Hyun Kim²,  Sung Kyu Lim^2
1Tsinghua University, ²Georgia Institute of Technology

Chair: Lech Jozwiak, Eindhoven University of Technology
Co-Chair: Rajesh Berigei, Texas Instruments

3:50PM
6C.1
Learning Based DVFS for Simultaneous Temperature, Performance and Energy Management
Hao Shen¹,  Jun Lu²,  Qinru Qiu^1
1Syracuse University, ²Binghamton University

4:10PM
6C.2
Hot Peripheral Thermal Management to Mitigate Cache Temperature Variation
Houman Homayoun¹,  Mehryar Rahmatian²,  Vasileios Kontoniris¹,  Shahin Golshan²,  Dean Tullsen^1
1University of California San Diego, ²University of California Irvine

4:30PM
6C.3
Power-Performance Yield Optimization for MPSoCs Using MILP
Kshitij Bhardwaj,  Sanghamitra Roy,  Koushik Chakraborty
Utah State University

4:50PM
6C.4
A Variation and Energy Aware ILP formulation for Task Scheduling in MPSoC
Mahboobeh Ghorbani
University of Southern California

5:10PM
6C.5
Register Binding and Domain Assignment for Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis
Keisuke Inoue and Mineo Kaneko
Japan Advanced Institute of Science and Technology