This paper investigates the circuit performance improvement through poly-pitch scaling in strain engineered devices. We use tensile contact etch stop liner(t-CESL), compressive contact etch stop liner(c-CESL), embedded SiC and SiGe as stress sources in NMOS and PMOS devices. It is observed that poly-pitch optimization delivers ~18% and ~13% reduction in delay of an inverter driving FO4 and FO1 loads respectively. We observe that, in the presence of process induced mechanical stress, the optimum poly-pitch depends upon the size of the driver and the load. Finally, we present a model for choosing optimum poly-pitch for enhanced circuit performance while taking care of the power constraint.