Dynamically biased low power High performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process

Abstract

Integration of legacy interfaces demand need for 3.3V I/Os in modern day SOCs. Low cost solutions exists by build 3.3V I/Os using specially biased 1.8V transistors imposing a serious limitation of trade-off between power, performance and reliability. This paper presents an I/O built using a dynamically biased differential amplifier based pre-driver circuit, with which excellent performance has been achieved up to 200MHz along with up to 30X reduction in power without compromise to reliability.