A post-fabrication dual supply voltage (VDD) control (PDVC) of multiple voltage domains is proposed for a minimum operating voltage (VDDmin)-limited ultra low voltage logic circuits. PDVC effectively reduces an average VDD below VDDmin, thereby reducing the power consumption of logic circuits. PDVC is applied to a DES CODEC’s circuit fabricated in 65nm CMOS. The layout of DES CODEC’s is divided into 64 VDD domains and each domain size is 54um x 63.2um. High VDD (VDDH) or low VDD (VDDL) is applied to each domain and the selection of VDD’s is performed based on multiple built-in self tests. VDDH is selected in VDDmin-critical domains, while VDDL is selected in VDDmin-non-critical domains. A maximum 24% power reduction was measured with the proposed PDVC at 300kHz, VDDH =437mV, and VDDL=397mV.