As CMOS technology is scaled down, the gate oxide is scaling aggressively. The defects in the gate oxide form traps over time and results in gate oxide break down. Time-dependent dielectric breakdown (TDDB) is considered as one of the most important reasons of performance variation of CMOS devices. Soft break down events do not cause immediate failure of the CMOS device but will affect the performance of the circuit, especially for future CMOS applications which are more susceptible to soft break down events. However, the reasons for delay variation (increase or decrease) after TDDB are not clear for researchers. In this paper, detail analysis and simulation results for the delay variation of digital circuit due to TDDB are demonstrated for different locations and levels using 32nm CMOS technology. In this paper, we show that the circuit delay can be increased or decreased depending on the input rising or falling transition of the circuit as well as the number of consecutive gates which are affected by TDDB.