Gating clocks has been a widely adopted technique for reducing dynamic power. The clock gating strategy employed has a huge bearing on the clock tree synthesis quality along with the impact to leakage and dynamic power. This paper proposes a technique for clock gate optimization to aid clock tree synthesis. The technique enables cloning and redistribution of the fanout among the existing equivalent clock gates. The technique is placement aware and hence reduces overall clock wire length and area. The method involves employing the ”k-means clustering algorithm” to geographically partition the design’s registers. This enables better clock tree quality entitlement during clock tree synthesis in terms of clock tree area, power and better local skew distribution. The paper highlights the utility of this technique by showcasing the clock tree synthesis quality of results improvement on a complex design.