As CMOS technology scales down, circuit performance has become even more sensitive to manufacturing and environmental variations. Thus, there is a need to measure or monitor circuit performance during manufacturing and at runtime. Since each circuit may have different sensitivities to process variations, previous works have focused on synthesis of circuit performance monitors that are specific to a given design. In this work, we study the potential benefit of having multiple (<10) design-dependent monitors. We develop a systematic approach to synthesis of multiple design-dependent monitors, as well as a corresponding delay estimation method. Our approach synthesizes design-dependent ring oscillators (DDROs) using standard library gates. This has the advantage of quick design turnaround time and reduced schedule impact, because the DDRO implementation can leverage automation in conventional implementation flows. Our delay estimation method seeks to minimize the number of parameters as well as computing resources (i.e., to limit information storage and exchange) used in delay estimation based on monitoring results. Experiments show that our delay estimation method using multiple DDROs reduces overestimation (timing margin) by up to 25% compared to use of a single replica path.