Network-on-Chip (NoC) design challenges such as high power consumption and high data transfer latencies are being addressed today with various novel solutions. Hybrid photonic on-chip interconnects are one such promising solution that balances various power and performance objectives. By implementing long distance communication with photonic waveguides and short distance communication with electrical interconnects, the performance and power bottlenecks associated with global on-chip transfers can be made more manageable. However, optimization of such interconnects to minimize power and latency requires traversing through a large design space. This process includes configuring design parameters such as wavelength division multiplexing (WDM), number of photonic uplinks, serialization degree, etc. Synthesizing application specific hybrid photonic NoCs to automate the configuring of these parameters is however an unexplored area so far. In this paper we propose an evolutionary algorithm framework to synthesize hybrid photonic NoCs by utilizing Particle Swarm Optimization (PSO) and Simulated Annealing (SA). Our synthesis results indicate that the PSO-based framework generates more power efficient NoC fabrics compared to Simulated Annealing (SA). The PSO synthesis approach optimizes the hybrid NoC fabric, achieving up to 18× power reduction compared to a traditional electrical NoC.