Chair: Kurt Schwartz, Texas Instruments
Co-Chair: Charles Augustine, Intel

10:20AM
1A.1
Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset
James Boley and Benton Calhoun
University of Virginia

10:40AM
1A.2
Designing Low-VTH STT-RAM for Write Energy Reduction in Scaled Technologies
Farah Yahya¹,  Mohammad Mansour²,  James Tschanz³,  Muhammad Khellah^3
1University of Virginia, Charlottesville VA, ²American University of Beirut, Lebanon, ³Intel Corp.

11:00AM
1A.3
High Performance and High Yield 5 nm Underlapped FinFET SRAM Design Using P type Access Transistors
Roohollah Yarmand¹,  Behzad Ebrahimi¹,  Hassan Afzali-Kusha²,  Ali Afzali-Kusha¹,  Massoud Pedram^2
1University of Tehran, ²University of Southern California

11:20AM
1A.4
Stability Analysis of Single-Ended Boost-Less Sub-threshold 7T FinFET SRAM Cell under Process-Voltage-Temperature Variations
Chandrabhan Kushwah¹,  Santosh Kumar Vishvakarma¹,  Devesh Dwivedi^2
1IIT Indore, ²IBM Bangalore

11:40AM
1A.5
An Energy-Efficient On-Chip Memory Structure for Variability-Aware Near-Threshold Operation
Jun Shiomi,  Tohru Ishihara,  Hidetoshi Onodera
Kyoto University

Chair: Srini Krishnamoorthy, AMD
Co-Chair: Vamsi Srikantam, Applied Micro

10:20AM
1B.1
Thermal Sensor Allocation for SoCs Based on Temperature Gradients
Jun Yong Shin,  Fadi Kurdahi,  Nikil Dutt
University of California Irvine

10:40AM
1B.2
Clock Skew Optimization for Maximizing Time Margin by Utilizing Flexible Flip-Flop Timing
Hyungjung Seo,  Jeongwoo Heo,  Taewhan Kim
Seoul National University

11:00AM
1B.3
Large-scale Multi-corner Leakage Optimization Under the Sign-off Timing Environment
George Gonzalez,  Murari Mani,  Mahesh Sharma
AMD

11:20AM
1B.4
Fast Obstacle-Avoiding Octilinear Steiner Minimal Tree Construction Algorithm for VLSI Design
Xing Huang,  Wenzhong Guo,  Guolong Chen
Fuzhou university

11:40AM
1B.5
A Router for Via Configurable Structured ASIC with Standard Cells and Relocatable IPs
Chiung-Chih Ho,  Hsin-Pei Tsai,  Liang-Chi Lai,  Rung-Bin Lin
Yuan Ze University

Chair: Rajan Beera, Pall Corporation
Co-Chair: Vivek Joshi, GLOBALFOUNDRIES

10:20AM
1C.1
Circuit Design Perspectives for Ge FinFET at 10nm and Beyond
S. Sinha¹,  L. Shifren²,  V. Chandra²,  B. Cline¹,  G. Yeric¹,  R. Aitken²,  B. Cheng³,  A. R. Brown³,  C. Riddet³,  C. Alexander³,  C. Millar³,  A. Asenov^3
1ARM Inc., Austin, TX, ²ARM Inc., San Jose, CA, ³Gold Standard Simulations Ltd., Glasgow, Scotland

10:40AM
1C.2
Electrical Characteristic and Power Consumption Fluctuations of Trapezoidal Bulk FinFET Devices and Circuits Induced by Random Line Edge Roughness
Chieh-Yang Chen,  Wen-Tsung Huang,  Yiming Li
National Chiao Tung University

11:00AM
1C.3
Design Optimization of Sense Amplifiers using Deeply-scaled FinFET Devices
Alireza Shafaei¹,  Yanzhi Wang¹,  Antonio Petraglia²,  Massoud Pedram^1
1University of Southern California, ²Federal University of Rio de Janeiro

11:20AM
1C.4
GlYFF: A Framework for Global Yield and Floorplan Aware Design Optimization
Shuo Wang,  Yue Gao,  Melvin Breuer
University of Southern California

11:40AM
1C.5
Method for Efficient Flash Bit Cell Current Compression in Deeply Erased Bits
Jon Nafziger and Dan Burggraf
Texas Instruments

Chair: Aswin Mehta, Texas Instruments
Co-Chair: Charles Augustine, Intel

1:30PM
2A.1
A Simplified Single-Inductor Dual-Output DC-DC Buck Converter Architecture with a Fully Digital Σ−Δ Based Controller
Nijad Anabtawi¹ and Rony Ferzli^2
1Intel Corporation, ²Arizona State University

1:50PM
2A.2
A CMOS Hysteretic DC-DC Buck Converter with a Low Output Ripple Voltage
Tae Jin Chung and Kwang Yoon
Inha University

2:10PM
2A.3
A 4-14 Gbps Inductor-Less Adaptive Linear Equalizer in 65nm CMOS Technology
Govardhana Rao Talluri,  Rakesh K K,  Maryam Shojaei Baghini
IIT Bombay

2:30PM
2A.4
A Digitally-Controlled Power-Aware Low-Dropout Regulator to Reduce Standby Current Drain in Ultra-Low-Power MCU
Kaushik Mazumdar¹,  Steven Bartling²,  Sudhanshu Khanna²,  Mircea Stan^1
1University of Virginia, ²Texas Instruments

2:50PM
2A.5
A Radiation-Hardened-By-Design Phase-Locked Loop Using Feedback Voltage Controlled Oscillator
Seok Min Jung and Janet Roveda
University of Arizona

3:10PM
2A.6
Design of a Sigma-Delta Modulator in Standard CMOS Process for Wide-Temperature Applications
Yucai Wang and Vamsy Chodavarapu
McGill University

Chair: Vivek Nandakumar, Synopsys, Inc.
Co-Chair: Hai (Helen) Li, University of Pittsburgh

1:30PM
2B.1
Architectural Reliability Estimation using Design Diversity
Zheng Wang¹,  Liu Yang¹,  Anupam Chattopadhyay^2
1RWTH-Aachen University, ²Nanyang Technological University

1:50PM
2B.2
Tabu Search Based Multiple Voltage Scheduling under both Timing and Resource Constraints
Jianmo Ni,  Nan Wang,  Takeshi Yoshimura
Waseda University

2:10PM
2B.3
Cache-Aware SPM Allocation Algorithms for Hybrid SPM-Cache Architectures
Lan Wu and Wei Zhang
Virginia Commonwealth University

2:30PM
2B.4
Task Partitioning Optimization Algorithm for Energy Saving and Load Balance on NoC-based MPSoCs
Marco Stefani,  Thais Webber,  Ramon Fernandes,  Rodrigo Cataldo,  Letícia Poehls,  César Marcon
PUCRS

2:50PM
2B.5
Improved Pipeline data Flow for DySER-based Platform
Zijian Hou¹,  Xin Chen²,  Weifeng He^1
1Shanghai Jiao Tong University, ²Tongji University

3:10PM
2B.6
Rapid Heterogeneous Prototyping from Simulink
Shen Feng,  Chris Driscoll,  Jerediah Fevold,  Hao Jiang,  Gunar Schirner
ECE, Northeastern University

Chair: Miroslav Velev, Aries Design Automation
Co-Chair: Jon Nafziger, Texas Instruments

1:30PM
2C.1
LBIST Pattern Reduction by Learning ATPG Test Cube Properties
Gustavo Contreras¹,  Yang Zhao¹,  Nisar Ahmed²,  LeRoy Winemberg²,  Mark Tehranipoor^1
1University of Connecticut, ²Freescale Semiconductor Inc.

1:50PM
2C.2
Preemptive Built-In Self-Test for In-Field Structural Testing
Panagiotis Sismanoglou,  Vlasis Pitsios,  Dimitris Nikolos
University of Patras

2:10PM
2C.3
A Scan Shifting Method based on Clock Gating of Multiple Groups for Low Power Scan Testing
Sungyoul Seo¹,  Yong Lee¹,  Joohwan Lee²,  Sungho Kang^1
1Department of Electronic Engineering, Yonsei University, Seoul, Korea, ²Samsung Electronics, Korea

2:30PM
2C.4
Designing Effective Scan Compression Solutions for Industrial Circuits
Subramanian Chebiyam,  Anshuman Chandra,  Rohit Kapur
Synopsys Inc

2:50PM
2C.5
Low Power Scan Bypass Technique with Test Data Reduction
Hyunyul Lim,  Wooheon Kang,  Sungyoul Seo,  Yong Lee,  Sungho Kang
Department of Electrical and Electronic Engineering Yonsei University, Seoul, Korea

3:10PM
2C.6
Incremental ATPG Methods for Multiple Faults under Multiple Fault Models
Masahiro Fujita¹,  Alan Mishchenko²,  Naoki Taguchi¹,  Kentaro Iwata^1
1University of Tokyo, ²University of California, Berkeley

Chair: Rangharajan Venkatesan, Texas Instruments
Co-Chair: Charles Augustine, Intel

3:50PM
3A.1
Energy Reduction by Built-in Body Biasing with Single Supply Voltage Operation
Norihiro Kamae,  A.K.M. Mahfuzul Islam,  Akira Tsuchiya,  Tohru Ishihara,  Hidetoshi Onodera
Kyoto University

4:10PM
3A.2
Design of an Incoherent IR-UWB Receiver Front-End in 180-nm CMOS Technology
Jihai Duan,  Qiangyu Hao,  Yu Zheng,  Baolin Wei,  Weilin Xu,  Shichao Xu
School of Information & Communication,Guilin University of Electronic Technology, Guilin, China

4:30PM
3A.3
Analysis and Optimization of Flip-Flops Under Process and Runtime Variations
Mohammad Saber Golanbari¹,  Saman Kiamehr¹,  Mehdi B. Tahoori¹,  Sani Nassif^2
1Karlsruhe Institute of Technology, ²Radyalis LLC

4:50PM
3A.4
Energy Efficient Design of DVB-T2 Constellation Demapper
Nourhan Bahgat,  DiaaEldin Khalil,  Salwa El-Ramly
ECE Department, Ain Shams University, Cairo, Egypt

5:10PM
3A.5
Advanced Encryption System with Dynamic Pipeline Reconfiguration for Minimum Energy Operation
Srivatsan Chellappa,  Chandarasekaran Ramamurthy,  Vinay Vashishtha,  Lawrence Clark
Arizona State University

Chair: Hai (Helen) Li, University of Pittsburgh
Co-Chair: Lei Wang, University of Connecticut

3:50PM
3B.1
Temperature Aware Refresh for DRAM Performance Improvement in 3D ICs
Menglong Guan and Lei Wang
Department of Electrical and Computer Engineering University of Connecticut

4:10PM
3B.2
Adaptive Tracking Channel Control for GNSS Receivers under Renewable Energy
Wenjie Huang and Lei Wang
University of Connecticut

4:30PM
3B.3
Novel SAT-based Invariant-Directed Low-Power Synthesis
Mahmoud Elbayoumi¹,  Michael Hsiao¹,  Mustafa Elnainay^2
1Virginia Tech, ²Alexanderia University

4:50PM
3B.4
Application and OS Unconscious Power Manager for SoC Systems
Hend Affes,  Amal Chaker,  Michel Auguin
University Nice Sophia Antipolis

5:10PM
3B.5
Orchestrated Application Quality and Energy Storage Management in Solar-Powered Embedded Systems
Nga Dang,  Hossein Tajik,  Nikil Dutt,  Nalini Venkatasubramanian,  Eli Bozorgzadeh
University of California, Irvine

Chair: Syed Alam, Everspin
Co-Chair: Saibal Mukhopadhyay, Georgia Tech

3:50PM
3C.1
Optimal Choice of FinFET Devices for Energy Minimization in Deeply Scaled Technologies
Mohammad Saeed Abrishami,  Alireza Shafaei,  Yanzhi Wang,  Massoud Pedram
University of Southern California

4:10PM
3C.2
Ultra-Fast Variability-Aware Optimization of Mixed-Signal Designs using Bootstrapped Kriging
Saraju Mohanty,  Elias Kougianos,  Venkata Yanambaka
University of North Texas

4:30PM
3C.3
Novel Technique for P-hit Single-Event Transient Mitigation using Enhance Dummy Transistor
Wang TianQi,  Xiao LiYi,  Huo MingXue,  Qi ChunHua,  Liu ShanShan
Harbin Institute of Technology

4:50PM
3C.4
Signal Domain Based Reachability Analysis in RTL Circuits
Sharad Bagri,  Kelson Gent,  Michael Hsiao
Virginia Tech

5:10PM
3C.5
Equivalence Checking of Scheduling in High-Level Synthesis
Tun Li,  Jian Hu,  Yang Guo,  Sikun Li,  Qingping Tan
NUDT

Chair: Peter Wright, Synopsys
Co-Chair: Saibal Mukhopadhyay, Georgia Institute of Technology

5:30PM
P.1
Design and Analysis of Low Pass Microstrip Filters using MATLAB
Luv Tomar¹,  Saurabh Gupta²,  Raghuvir Tomar³,  Prakash Bhartia^4
1Carleton University, ²Neutrino IT Technologies, ³The LNM Institute of Information Technology, ⁴NATEL Engineering Co., Inc.

5:30PM
P.2
Employing Dynamic Body-Bias for Short Circuit Power Reduction in SRAMs
Yakup Murat mert¹ and Osman Seckin simsek^2
1TUBİTAK İLTAREN, ²ODTU

5:30PM
P.3
Accurate Standard Cell Characterization and Statistical Timing Analysis using Multivariate Adaptive Regression Splines
Taizhi Liu,  Chang-Chih Chen,  Linda Milor
Georgia Institute of Technology

5:30PM
P.4
A Fault Prediction Module for a Fault Tolerant NoC Operation
Jarbas Silveira¹,  Mathieu Bodin²,  João Marcelo Ferreira¹,  Alan Cadore Pinheiro¹,  Thais Webber³,  César Marcon^4
1LESC-DETI, ²Polytechnique Nice-Sophia, ³PPGEE/PUCRS, ⁴PPGCC/PUCRS

5:30PM
P.5
User Power-Delay Budget Driven PSO Based Design Space Exploration of Optimal k-cycle Transient Fault Secured Datapath during High Level Synthesis
Anirban Sengupta and Saumya Bhadauria
Indian Institute of Technology, Indore

5:30PM
P.6
A Distinctive O(mn) Time Algorithm for Optimal Buffer Insertions
Xinsheng Wang¹,  Wenpan Liu¹,  Mingyan Yu^2
1Harbin Institute of Technology, ²Ningbo Institute of Technology Zhejiang University

5:30PM
P.7
Design and Analysis of Novel SRAM PUFs with Embedded Latch for Robustness
Jae-Won Jang and Swaroop Ghosh
University of South Florida

5:30PM
P.8
Fast Synthesis of Low Power Clock Trees Based on Register Clustering
Chao Deng,  Yici Cai,  Qiang Zhou
Tsinghua University

5:30PM
P.9
Irregularly Shaped Voltage Islands Generation with Hazard and Heal Strategy
Zhen Meng,  Song Chen,  Lu Huang
Department of Electronic Science and Technology, USTC, China

5:30PM
P.11
Impact of Geometry Parameter on Electromigration Reliability in FCBGA Package
Lihua Liang¹,  Yuanxiang Zhang²,  Richard Rao^3
1Zhejiang University of Technology, ²Quzhou University, ³Vitesse Semiconductor Corporation

5:30PM
P.12
Enhancing System-Wide Power Integrity in 3D ICs with Power Gating
Hailang Wang and Emre Salman
Stony Brook University

5:30PM
P.13
Design of a Low-power UHF RFID Tag Baseband with Three-level Clock-gating Technique
Haibo Liao¹,  Bin Wang¹,  Weixin Kong²,  Yonghua Hu²,  Hui Du^2
1Hangzhou Dianzi University, ²Rice Microelectronics Co. Ltd.

5:30PM
P.14
Temperature-aware Thread Assignment of Many-core Processor
S. Xuan¹ and Y. Yang^2
1Fudan University, ²GPIX Inc

5:30PM
P.15
Separation of Concerns for Hardware Components of Embedded Systems in BIP
Maya Safieddine¹,  Rouwaida Kanj¹,  Fadi Zaraket¹,  Ali Elzein²,  Mohamad Jaber^1
1American University of Beirut, ²IBM

5:30PM
P.16
Unreachable Code Identification For Improved Line Coverage
Luke Pierce and Spyros Tragoudas
Southern Illinois University

5:30PM
P.17
Efficient Task Partitioning and Scheduling for Thermal Management in Multicore Processors
Zhe Wang,  Sanjay Ranka,  Prabhat Mishra
University of Florida

Chair: Steve Heinrich-Barna, Texas Instruments
Co-Chair: Charles Augustine, Intel

10:20AM
4A.1
Fail-Safe I/O to Control RESET# Pin of DDR3 SDRAM and Achieve Ultra-Low System Power
Rajat Chauhan,  Prajkta Vyavahare,  Siva Kothamasu
Texas Instruments

10:40AM
4A.2
On-Line Reliability-Aware Dynamic Power Management for Real-Time Systems
Ming Fan¹,  Qiushi Han²,  Shuo Liu²,  Gang Quan^2
1Broadcom Corporation, ²Florida International University

11:00AM
4A.3
Design and Performance Parameters of an Ultra-Low Voltage, Single Supply 32bit Processor Implemented in 28nm FDSOI Technology
Sylvain Clerc¹,  Fady Abouzeid¹,  Darayus Adil Patel¹,  Jean-Marc Daveau¹,  Cyril Bottoni¹,  Lorenzo Ciampolini¹,  Fabien Giner¹,  David Meyer¹,  Robin Wilson¹,  Philippe Roche¹,  Sylvie Naudet¹,  Arnaud Virazel²,  Alberto Bosio²,  Patrick Girard^2
1STMicroelectronics, ²LIRMM

11:20AM
4A.4
Efficient Static D-Latch Standard Cell Characterization Using a Novel Setup Time Model
Arvind Sharma¹,  Yogendra Sharma²,  Sudeb Dasgupta¹,  Bulusu Anand^1
1IIT Roorkee, ²Synopsis India Pvt. Ltd.

11:40AM
4A.5
TDTB Error Detecting Latches: Timing Violation Sensitivity Analysis and Optimization
Matheus Moreira¹,  Dylan Hand²,  Peter Beerel²,  Ney Calazans^1
1PUCRS, ²USC

Chair: Houman Houmayoun, George Mason University
Co-Chair: Lei Wang, University of Connecticut

10:20AM
4B.1
Adaptive Mode Assignment in Performance-critical Cyber-physical Systems
Zhaohui Yuan,  Rong Zhu,  Yiqin Cao,  Guifen Jiang
East China Jiaotong University

10:40AM
4B.2
Trading-Off System Load and Communication in Mapping Heuristics for Improving NoC-based MPSoCs Reliability
Marcelo Mandelli¹,  Luciano Ost²,  Gilles Sassatelli³,  Fernando Moraes^1
1PUCRS, ²University of Leicester, ³LIRMM

11:00AM
4B.3
A 2-Layer Laser Multiplexed Photonic Network-on-Chip
Dharanidhar Dang,  Biplab Patra,  Rabi N. Mahapatra
Texas A&M University

11:20AM
4B.4
Exploring Shared Memory and Cache to Improve GPU Performance and Energy Efficiency
Hao Wen and Wei Zhang
Virginia Commonwealth University

11:40AM
4B.5
Enhancing Performance of Wireless NoCs with Distributed MAC Protocols
Karthi Duraisamy,  Ryan Kim,  Partha Pande
Washington State University

Chair: Vinod Viswanath, Real Intent
Co-Chair: Sreejit Chakravarty, Intel Corporation

10:20AM
4C.1
Exploiting Abstraction, Learning from Random Simulation, and SVM Classification for Efficient Dynamic Prediction of Software Health Problems
Miroslav N. Velev¹,  Chaoqiang Zhang²,  Ping Gao¹,  Alex D. Groce^2
1Aries Design Automation, ²Oregon State University

10:40AM
4C.2
Optimum Domain Partitioning to Increase Functional Verification Coverage
Jomu George Mani Paret and Otmane Ait Mohamed
Concordia University

11:00AM
4C.3
Crosstalk-Aware Signal Probability-Based Dynamic Statistical Timing Analysis
Yao Chen¹,  Andrew Kahng²,  Bao Liu¹,  Wenjun Wang^1
1University of Texas at San Antonio, ²University of California, San Diego

11:20AM
4C.4
A Low Area Calibration Technique of TDC using Variable Clock Generator for Accurate On-Line Delay Measurement
Kentaroh Katoh¹ and Kazuteru Namba^2
1National Institute of Technology, Tsuruoka College, ²Chiba University

11:40AM
4C.5
Near Optimal Repair Rate Built-in Redundancy Analysis with Very Small Hardware Overhead
Woosung Lee,  Keewon Cho,  Jooyoung Kim,  Sungho Kang
Department of Electrical & Electronic Engineering, Yonsei University, Seoul Korea

Chair: Xuehui Zhang, Oracle
Co-Chair: Bao Liu, University of Texas at San Antonio

1:00PM
5A.1
A Survey on Memristor Modeling and Security Applications
M. T. Arafin¹,  C Dunbar¹,  G. Qu¹,  N. McDonald²,  L. Yan^2
1University of Maryland, ²Air Force Research Laboratory

1:20PM
5A.2
Digital PUF using Intentional Faults
Teng Xu and Miodrag Potkonjak
UCLA

1:40PM
5A.3
Side Channel Attacks in Embedded Systems: A Tale of Hostilities and Deterrence.
Jude Angelo Ambrose¹,  Roshan G. Ragel²,  Darshana Jayasinghe¹,  Tuo Li¹,  Sri Parameswaran^1
1The University of New South Wales, ²University of Peradeniya

2:00PM
5A.4
Fault-Tolerant Methods for a New Lightweight Cipher Code SIMON
Jaya Dofe¹,  Connor Reed²,  Ning Zhang³,  Qiaoyan Yu^1
1University of New Hampshire, ²Nashua North High School, ³Xidian University

2:20PM
5A.5
Novel Self-Calibrating Recycling Sensor using Schmitt-Trigger and Voltage Boosting for Fine-Grained Detection
Cheng Wei Lin and Swaroop Ghosh
University of South Florida

2:40PM
5A.6
The Low Power Design of SM4 Cipher with Resistance to Differential Power Analysis
Yanbo Niu and Anping Jiang
Beijing Microelectronic Technology Institute

Chair: Rajesh R. Berigei, Texas Instruments, Inc.
Co-Chair: Vivek Nandakumar, Synopsys, Inc

1:00PM
5B.1
Comparative Evaluation of FPGA and ASIC Implementations of Bufferless and Buffered Routing Algorithms for On-Chip Networks
Yu Cai,  Ken Mai,  Onur Mutlu
Carnegie Mellon University

1:20PM
5B.2
Hardened Design Based on Advanced Orthogonal Latin Code against Two Adjacent Multiple Bit Upsets (MBUs) in Memories
Liyi Xiao,  Jiaqiang Li,  Jie Li,  Jing Guo
Microelectronics Center, Harbin Institute of Technology, Harbin, 150001, China

1:40PM
5B.3
Scratch-Pad Memory Banking by Dynamic Programming for Embedded Data-Intensive Applications
Florin Balasa¹,  Noha Abuaesh¹,  Ilie I. Luican²,  Hongwei Zhu^3
1American University in Cairo, Egypt, ²Microsoft, USA, ³ARM, USA

2:00PM
5B.4
A Hypervisor Approach with Real-time Support to the MIPS M5150 Processor
Samir Zampiva,  Carlos Moratelli,  Fabiano Hessel
PUCRS

2:20PM
5B.5
RT-MIL-STD-1553+: Remote Terminal Controller for MIL-STD-1553B at 100-Mb/s Data Rate
Prateek Pendyala¹ and Vijaya Sankara Rao Pasupureddi^2
1IIIT Hyderabad, ²IIT Ropar

2:40PM
5B.6
Low Power Scheduling in High-level Synthesis using Dual-Vth Library
Samaneh Ghandali,  Bijan Alizadeh,  Zainalabedin Navabi
University of Tehran

Chair: Farhang Yazdani, BroadPak
Co-Chair: Paul Franzon, NCSU

1:00PM
5C.1
A Novel Approach to IC, Package, and Board Co-Optimization
Gary Brist¹ and John Park^2
1Intel, ²Mentor Graphics

1:20PM
5C.2
An Effective Model for Evaluating Vertical Propagation Delay in TSV-based 3-D ICs
Masayuki Watanabe,  Nanako Niioka,  Tetsuya Kobayashi,  Rosely Karel,  Masa-aki Fukase,  Masashi Imai,  Atsushi Kurokawa
Hirosaki University

1:40PM
5C.3
Automatic Die Placement and Flexible I/O Assignment in 2.5D IC Design
Daniel Seemuth,  Azadeh Davoodi,  Katherine Morrow
University of Wisconsin - Madison

2:00PM
5C.4
Resource Allocation Methodology for Through Silicon Vias and Sleep Transistors in 3D ICs
Hailang Wang and Emre Salman
Stony Brook University

2:20PM
5C.5
Recovery of Faulty TSVs in 3D ICs
Surajit Kumar Roy,  Kaustav Roy,  Chandan Giri,  Hafizur Rahaman
Dept. of Information Technology, IIEST, Shibpur

2:40PM
5C.6
Novel Adaptive Power Gating Strategy of TSV-based Multi-layer 3D IC
Seungwon Kim,  Seokhyeong Kang,  Ki Jin Han,  Youngmin Kim
Ulsan National Institute of Science and Technology, Republic of Korea

Chair: James Lei, Ominvision
Co-Chair: Xiaoning Qi, Intel

3:20PM
6A.1
A Low-Power Field-Programmable Analog Array for Wireless Sensing
Brandon Rumberg and David Graham
West Virginia University

3:40PM
6A.2
On Improving the Range of Inductive Proximity Sensors for Avionic Applications
Paul Leons¹,  Aryan Yaghoubian¹,  Glenn Cowan¹,  Jelena Trajkovic¹,  Yvon Nazon²,  Samar Abdi^1
1Concordia University, ²Thales Avionics

4:00PM
6A.3
A New Single Inductor Bipolar Multiple Output (SIBMO) Boost Converter Using Pulse Frequency Modulation (PFM) Control for OLED Drivers and Optical Transducers
Chun-Kai Chang¹,  Chung-Hsin Su²,  Yung-Hua Kao¹,  Ming-Hung Yu¹,  Thilo Sauter³,  Paul Chao^1
1Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan, ²Sitronix Technology Corporation, ³Center for Integrated Sensor Systems, Danube University Krems, Austria

4:20PM
6A.4
RFID Indoor Localization Based on Doppler Effect
Deivid Antunes Tesch,  Everton Luís Berz,  Fabiano Passuelo Hessel
PUCRS

4:40PM
6A.5
A Novel Physical Failure Analysis of MEMS Motion Sensor for Interface Inspection
Chunan Huang¹,  Li Chuang¹,  Kim Hsu¹,  Steel Chung²,  Tim Chan^2
1Integrated Service Technology, ²Richtek Technology

Chair: Ofelya Manukyan, Synopsys
Co-Chair: Abishai Daniel, Intel Corp.

3:20PM
6B.1
Exploring Memory Controller Configurations for Many-Core Systems with 3D Stacked DRAMs
Fen Ge¹,  Jia Zhan²,  Yuan Xie²,  Vijaykrishnan Narayanan^3
1Nanjing University of Aeronautics and Astronautics, China, ²University of California at Santa Barbara, U.S.A., ³The Pennsylvania State University, U.S.A.

3:40PM
6B.2
Virtual Logic Netlist: Enabling Efficient RTL Analysis
Spandana Rachamalla,  Arun Joseph,  Rahul Rao,  Diwesh Pandey
IBM

4:00PM
6B.3
A Logic Difference Generator with Spare Cells Consideration for ECO Synthesis
Jui-Hung Hung¹,  Yu-Cheng Lin²,  Wei-Kai Cheng¹,  Tsai-Ming Hsieh^1
1Chung Yuan University, ²Kainan University

4:20PM
6B.4
Cells Reconfiguration around Defects in CMOS/Nanofabric Circuits using Simulated Evolution Heuristic
Abdalrahman M. Arafeh¹ and Sadiq M. Sait^2
1University of British Columbia, ²King Fahd University of Petroleum & Minerals

4:40PM
6B.5
Layout-aware Analog Synthesis Environment with Yield Consideration
Hsin-Ju Chang,  Yen-Lung Chen,  Conan Yeh,  Chien-Nan Liu
National Central University

Chair: Paul Tong, Pericom Semiconductor
Co-Chair: Yiran Chen, University of Pittsburg

3:20PM
6C.1
A Comparative Analysis of Symmetric and Asymmetric Dual-k Spacer FinFETs from Device and Circuit Perspectives
Pankaj Pal,  Brajesh Kaushik,  Bulusu Anand,  Sudeb Dasgupta
IIT Roorkee

3:40PM
6C.2
Technology/Circuit Co-optimization and Benchmarking for Graphene Interconnects at Sub-10nm Technology Node
Chenyun Pan¹,  Praveen Raghavan²,  Francky Catthoor²,  Zsolt Tokei²,  Azad Naeemi^1
1Georgia Institute of Technology, ²IMEC

4:00PM
6C.3
Domain Wall Motion-based Low Power Hybrid Spin-CMOS 5-bit Flash Analog Data Converter
Karthik Yogendra,  Mei-Chin Chen,  Xuanyao Fong,  Kaushik Roy
Purdue University

4:20PM
6C.4
6-T SRAM Performance Assessment with Stacked Silicon Nanowire MOSFETs
Ya-Chi Huang¹,  Meng-Hsueh Chiang²,  Wei-Chou Hsu²,  Shiou-Ying Cheng^1
1National Ilan University, ²National Cheng Kung University

4:40PM
6C.5
Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor (PD-SOFFET).
Azzedin Es-Sakhi and Masud Chowdhury
University of Missouri – Kansas City