The design of high performance SRAM in scaled technology nodes has become challenging due to an increase in both variation and leakage. The sense amplifier is one component that is particularly sensitive to threshold voltage variation due to its symmetrical design. Reducing the intrinsic input-referred offset of the sense amp reduces the bitline development time, which improves both energy and delay. In this paper we present a source coupled scheme that requires no area overhead and reduces the standard deviation of offset (σOFFSET) by up to 19%. In addition we present three novel sense amp designs that offer up to a 48% reduction in offset at iso-area compared to a traditional latch-based design.