Functional test generation and reachability analysis are challenging problems for today’s complex circuits. This paper proposes a novel analysis based on the domain of signal values in the register-transfer level (RTL) code of the circuit to reason about the reachability of all basic blocks in the RTL code. This analysis is able to resolve the question of reachability without explicit circuit unrolling. It can identify more unreachable branches quickly and can also provide guidance for which code blocks should be executed in order to reach a target condition.