This paper concentrates on the problem of minimizing power consumption during scheduling in high-level synthesis using a dual threshold voltage (dual-Vth) technique. In the proposed method, first all the operations are initialized to high-Vth, which generally cause violations of timing constraints. Then a set of operations are reassigned to low-Vth to meet the latency constraint in such a way that: 1) all existing slacks in the data-flow graph are utilized, 2) the leakage power is minimized and 3) the latency constraints are met. Our experimental results have shown an average improvement of 64.97% in runtime compared with the state-of-the-art technique, and an average improvement of 48.30% in leakage power consumption compared with the original designs.