This work proposes an extension of the MIL-STD-1553B remote terminal controller:RT-MIL-STD-1553+, which can process 100-Mb/s data over 1553 buses. This redesigned controller has three major architectural enhancements over the current 1-Mb/s controllers. Firstly, it incorporates a synchronous back-end and host processor interface to a true dual port memory to enable faster memory accesses. Secondly, the controller employs a majority-based sampling free-running decoder, suitable to interface to 100-Mb/s analog transceivers. Thirdly, the remote terminal protocol control unit has scaled-up state machines to manage the scheduling, storage and retrieval of 1553 messages, thus ensuring this increased throughput. The proposed remote terminal controller has been implemented in 1.2V, 65-nm CMOS technology. Performance results shows a power consumption of 14.59 mW at 100-Mb/s data rate for a 100 percent duty cycle, occupying an area of 104981 mm2, for a target BER of 10^-12.