ISQED'20 Embedded Tutorials
Chair & Moderators:
Shiyan Hu - Michigan Technological University (Chair)
José Pineda de Gyvez - NXP Semiconductors (Co-Chair)
Steven Hsu - Intel Corporation (Co-Chair)
Tutorial 1
Wednesday, March 25, 1:00PM-2:00PM
Abundant-Data Computing: The N3XT 1,000X
Presenter:
Prof. Subhasish Mitra, Stanford University
Subhasish Mitra Abstract: The world’s appetite for analyzing massive amounts of data (streaming video and audio, natural languages, real-time sensor readings, contextual environments or even brain signals) is growing dramatically. The computation demands of these abundant-data applications, such as machine learning, far exceed the capabilities of today’s computing systems, and can no longer be met by isolated improvements in transistor technologies, memories or integrated circuit architectures alone. To achieve unprecedented functionality, speed and energy efficiency, one must create transformative NanoSystems which exploit unique properties of underlying nanotechnologies to implement new architectures. We will present the N3XT (Nano-Engineered Computing Systems Technology) approach that enables such NanoSystems through: (i) new computing system architectures leveraging emerging device (logic and memory) nanotechnologies and their dense 3D integration with fine-grained connectivity for computation immersed in memory, (ii) new logic devices (such as carbon nanotube field-effect transistors for implementing high-speed and low-energy logic circuits) as well as high-density non-volatile memory (such as resistive RAM that can store multiple bits inside each memory cell), amenable to (iii) ultra-dense (monolithic) 3D integration of thin layers of logic and memory devices that are fabricated at low temperature. In addition, special techniques overcome imperfections, variations and reliability challenges in such logic, memory and 3D integration technologies. A wide variety of N3XT hardware prototypes (built in research facilities and also in US foundry as part of DARPA’s 3DSoC program) represent leading examples of transforming scientifically-interesting nanomaterials and nanodevices into actual NanoSystems. N3XT NanoSystems target 1,000X system-level energy-delay product benefits especially for abundant-data applications. Such massive benefits enable a wide range of applications that push new frontiers, from deeply-embedded computing systems all the way to the cloud.
About Subhasish Mitra
Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University. He directs the Stanford Robust Systems Group, co-leads the Computation focus area of the Stanford SystemX Alliance, and is a faculty member of the Wu Tsai Neurosciences Institute. Prof. Mitra also holds the Carnot Chair of Excellence in NanoSystems at CEA-LETI in Grenoble, France. His research ranges across robust computing, NanoSystems, Electronic Design Automation, and neurosciences. Results from his research group have been widely deployed by industry and have inspired significant development efforts by government and research organizations in multiple countries.
Jointly with his students and collaborators, Prof. Mitra demonstrated the first carbon nanotube computer and the first three-dimensional NanoSystem with computation immersed in data storage. These demonstrations received wide-spread recognition: cover of NATURE, Research Highlight to the United States Congress by the National Science Foundation, and highlight as "important, scientific breakthrough" by news organizations around the world.
In the field of robust computing, Prof. Mitra and his students created key approaches for soft error resilience, circuit failure prediction, on-line self-test and diagnostics, and QED (Quick Error Detection) design verification and system validation. His earlier work on X-Compact test compression at Intel Corporation has proven essential to cost-effective manufacturing and high-quality testing of almost all electronic systems across the industry. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools.
Prof. Mitra's honors include the ACM SIGDA / IEEE CEDA Newton Technical Impact Award in Electronic Design Automation (a test of time honor), the Semiconductor Research Corporation's Technical Excellence Award (for innovation that significantly enhances the semiconductor industry), the Intel Achievement Award (Intel’s highest corporate honor), and the United States Presidential Early Career Award for Scientists and Engineers from the White House. He and his students have published award-winning papers at major venues: ACM/IEEE Design Automation Conference, IEEE International Solid-State Circuits Conference, ACM/IEEE International Conference on Computer-Aided Design, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. At Stanford, he has been honored several times by graduating seniors "for being important to them during their time at Stanford."
Prof. Mitra has served on the Defense Advanced Research Projects Agency's (DARPA) Information Science and Technology Board as an invited member. He is a Fellow of the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE).
Tutorial 2
Wednesday, March 25, 2:00PM-3:00PM
Energy-efficient Secure Circuits for Entropy Generation & Cryptography
Presenter:
Dr. Sanu Mathew, Senior Principal Engineer, Intel
Sanu MathewAbstract: Physically Unclonable Functions (PUF) and True Random Number Generators (TRNG) are foundational security primitives underpinning the root of trust in computing platforms. Contradictory design strategies to harvest static and dynamic entropies typically necessitate independent PUF and TRNG circuits, adding to design cost. This tutorial describes a unified static and dynamic entropy generator leveraging a common entropy source for simultaneous PUF and TRNG operation. We will present self-calibration techniques to run-time segregate bitcells into PUF and TRNG candidates, along with entropy extraction techniques to maximize TRNG entropy while stabilizing PUF bits. Cryptographic circuits such as Advanced Encryption Standard (AES) are vulnerable to correlation power analysis (CPA) side-channel attacks (SCA), where an adversary monitors supply current signatures of a chip to decipher the value of embedded keys. This tutorial will also discuss the use of arithmetic/circuit countermeasures to minimize the correlation of the AES current to embedded keys, thereby improving the SCA resistance of the hardware by 1200x in both time and frequency-domains.
About Sanu Mathew
Sanu Mathew is a Senior Principal Engineer with the Circuits Research Labs at Intel Corporation, Hillsboro, Oregon, where he heads the security arithmetic circuits research group, responsible for developing special-purpose hardware accelerators for cryptography and security. He received his Ph.D. degree in Electrical and Computer Engineering from State University of New York at Buffalo in 1999. He holds 62 issued patents, has 20 patents pending and has published over 80 conference/journal papers. He is a Fellow of the IEEE.
Tutorial 3
Thursday, March 26, 1:00PM-2:00PM
EDA for Quantum Computing
Presenter:
Dr. Leon Stok, IBM Corp., Poughkeepsie, NY
Leon Stok Abstract: Though early in its development, quantum computing is now available on real hardware via the cloud through IBM Q Experience. This radically new kind of computing holds open the possibility of solving some problems that are now and perhaps always will be intractable for “classical” computers. As with any new technology there are a lot of open questions. What is the road to Quantum Advantage, e.g. the point where quantum computing shows demonstrable and significant advantage over classical computers and algorithms? What is the status of Quantum computers today? How do we define a full system-metric to measure the performance of a Quantum System? We will discuss what we can do in EDA to improve the performance of Quantum Systems and describe the types of EDA problems where quantum computing might be applied.
About Leon Stok
Leon Stok is Vice President of IBM's Electronic Design Automation group. His team delivers world-class design and verification flows and tools being used to design the world’s largest supercomputers, IBM systemZ and Power systems. Prior to this he held positions as director of EDA and executive assistant to IBM's Senior Vice President of Technology and Intellectual Property and executive assistant to IBM's Senior Vice President of the Technology group. Leon Stok studied electrical engineering at Eindhoven University of Technology, the Netherlands, from which he graduated with honors in 1986. He obtained a Ph.D. degree from Eindhoven University in 1991. At IBM's Thomas J. Watson Research Center, Leon Stok pioneered logic synthesis, as part of the team that developed BooleDozer. Subsequently, he managed IBM's synthesis group and drove the first commercial application of physical synthesis by developing IBM’s Placement Driven Synthesis tool. From 1999-2004 he led all of IBM's design automation research as the Senior Manager Design Automation at IBM Research. He drove key innovations in DFM using RDR (Radically Design Restrictions), in static timing analysis using statistical timing and in large block physical synthesis. Dr. Stok has presented over sixty keynotes, invited talks and tutorials at major IEEE and ACM conferences worldwide and at many leading universities. Dr. Stok has published over sixty papers on many aspects of high level, architectural and logic synthesis, low power design, placement driven synthesis and on the automatic placement and routing for schematic diagrams. He holds 13 patents in EDA. He was elected an IEEE fellow for the development and application of high-level and logic synthesis algorithms.
Tutorial 4
Thursday, March 26, 2:00PM-3:00PM
Bitcoin Demystified: Disrupting Technology or Mafia Haven?
Presenter:
Dr. Eric Peeters, Texas Instruments
Eric PeetersAbstract: In this tutorial, we will focus on how bitcoin actually works. Essentially we will cover what is a blockchain. What does “mining coin” mean and how distributed consensus can be achieved. We will cover quickly 2 important concepts in cryptography that enables this technology: hash and signature. We will also discuss attacks that were carried out to stole bitcoins in the past, how and if bitcoin can be used for illegal transactions and finally we will discuss the cost of bitcoins and some alternatives and try to compare it with major centralized existing systems like Visa or Mastercard.
About Eric Peeters
Dr. Eric Peeters received the ME degree in electro-mechanical engineering from University of Louvain-la-Neuve, Belgium, in 2002, and the MSc. and Ph.D. degrees in electrical engineering from the same University in 2004 and 2006, respectively. In 2006, he joined the group Thales Alenia Space ETCA in Belgium for around 1 year. Then, in September 2007, he joined TI Germany in Freising (Munich) to work on the development of security products. In September 2010, he moved to TI headquarters in Dallas where he has been leading the Connected MCU Embedded security group since October 2011 as Security Architect and Manager.