Keynotes at ISQED 2010

High Rel by Design - Creating Enterprise Class Memories

Ramanan Thiagarajah
Sr. Director of Product and Test Engineering
Inphi Corp

Enterprise class memory requirements are quickly outpacing the cost/density value curve. While DRAM $/bit is cheap, enabling high density solutions produces a technical and manufacturing challenge. With shorter product development and technology cycles for enterprise memory solutions, design quality and system integration is becoming increasingly important. The talk will take a holistic look at the role of DFm as it applies to product definition through end-of-life and the intricate balance between product robustness and time-to-market.

About Ramanan Thiagarajah

Ramanan Thiagarajah, as Director of Product & Test Engineering at Inphi, oversees new product introduction, manufacturing, strategic sourcing and product qualification across the breadth of Inphi products. Ramanan has over 13 years of experience in the semiconductor industry across a variety of functions spanning product/test engineering, applications engineering, marketing and business management. He started his career in 1998 at Vitesse Semiconductor. In mid-2001, he joined Inphi Corporation and helped structure the backend manufacturing process for both their Broadband Analog and Server & Storage businesses. Ramanan most recently was the product line manager for the Server & Storage business line at Inphi. Ramanan received his MBA with honors from the UCLA Anderson School of Management and his BSEE from the UCLA School of Engineering.

The New Challenges of Advanced SoC Implementation

Shankar Krishnamoorthy
Chief Scientist, Place & Route Division
Mentor Graphics

With the advent of advanced process nodes, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SOCs. However, design challenges are growing as we push the limits of complexity, size, power reduction, and manufacturing scaling. These challenges, if left unaddressed, can result in an adverse impact to schedule and designer productivity. Designers need a new generation of physical design tools to effectively address issues such as multi-mode multi-corner design closure, optimization for low power, compensating for manufacturing variability and handling the sheer magnitude of billion-transistor designs. They also need tools that take advantage of the latest multi-core processors for rapid turnaround, and enable seamless chip assembly at the full-chip level. Mr. Krishnamoorthy’s talk will describe the new requirements for physical design tools and how innovative approaches can make designers successful in the era of “manufacturing aware” design. Examples from a variety of design applications, including HDTV, graphics and mobile processors illustrate this highly informative presentation

About Shankar Krishnamoorthy

Shankar Krishnamoorthy has over 18 years of experience in the EDA industry leading world-class R&D teams that have delivered the industry’s leading physical design and logic synthesis solutions. He is presently Chief Scientist of the Place & Route Division at Mentor Graphics Corp. where he oversees the research, development and deployment of Mentor’s P&R solutions. He joined Mentor Graphics in 2007 as a result of a merger with Sierra Design Automation, a provider of digital physical design solutions. At Sierra Design Automation, he was Founder , Chief Technical Officer and VP of Engineering. Under his leadership, Sierra successfully delivered a next-generation physical design solution, Olympus-SoC, that addressed many of the key design challenges at advanced process nodes. Prior to Sierra, Mr. Krishnamoorthy was at the helm of the Physical Synthesis R&D organization at Synopsys Inc. where he conceived, architected and delivered Physical CompilerTM, the industry-standard physical synthesis product, at the time. He also led the Design Compiler™ R&D group at Synopsys Inc., continually delivering the best logic synthesis technology in the industry. Mr. Krishnamoorthy received his Masters in Computer Science from University of Texas at Austin and Bachelors in Computer Science from Indian Institute of Technology, Bombay, India.

Beyond Endless Verification: Delivering High Quality at Low Expense

Mark Gogolewski
CTO & CFO
Denali Software

Everyone is familiar with the skyrocketing costs of verification. Denali Software faced the same challenge when tackling the verification of their configurable controller for PCI Express, one of the most complex and wide-spread interface protocols. As a commercial provider of IP, quality could not be sacrificed. At the same time, the business model could not support a huge design and verification team, nor wait forever. In this keynote, Denali CTO Mark Gogolewski will center on how a small group of talented, highly motivated engineers was able to consistently deliver one of the industry’s most complex IP cores, reliably and on-time.

About Mark Gogolewski

Mark Gogolewski, a 15-year veteran of the semiconductor industry, has served Denali in many capacities since co-founding the company in 1996. He oversees all of the company's finance and accounting activities and is directly responsible for controllership, tax, treasury, analysis, investor relations, internal controls, internal audit and financial operations. His extensive experience also includes leading the development of key simulation and verification technologies focused on advanced memory system design and verification and the industry's first configurable memory controller core solution. Mr. Gogolewski has a BS in Applied Mathematics and an MS in Engineering Physics from the University of Virginia.

Test of the Future - Some Thoughts for the Next Decade

Antun Domic
Senior Vice President and General Manager
Synopsys

Over the last 40 years, test has moved from being a fab tool to being a design tool, and has become an integral part of the design flow. This move has allowed better (QOR), cheaper (COR), and faster (TTR) test.

As the vanguards of the semiconductor industry approach the 32-nanometer node and start planning the jump to the 22-nanometer node, a number of fundamental challenges are emerging, which force a thorough rethinking of the role of test. Like drugs, which often have counter-indications and side effects, even nanometer design and manufacturing are not immune to drawbacks. This requires that test assume an equal station to nanometer design and manufacturing, is accounted for by them, and inter-operates thoroughly with them. Both implementation and yield management tools may feed test with the design and manufacturing-related information it needs to keep problems manageable, while guaranteeing the desired quality and cost of results. At the same time, test can feed implementation and manufacturing with a great deal of information, which can help identify, locate, fix and/or prevent yield issues. In this keynote, Dr. Domic will describe how design, manufacturing, and test can join forces, and “collaborate” to battle the nanometer challenges.

About Antun Domic

Dr. Antun Domic joined Synopsys in April of 1997. In his current position, Dr. Domic manages the Implementation Group, responsible for Synopsys’ flagship synthesis and physical implementation solutions, physical verification, test automation, signal integrity, power and timing analysis, and formal verification products. Before joining Synopsys, Dr. Domic spent several years at Cadence Design Systems, where he was engineering vice president for the synthesis, place and route, and timing analysis areas. Previously, he worked in the microprocessor group of Digital Equipment Corporation in Hudson, Massachusetts, where he managed the development of CAD tools for synthesis and automatic layout used to design several generations of Alpha and VAX microprocessors. Prior to joining Digital, he worked at MIT Lincoln Laboratories and Honeywell Information Systems. Through the years, Dr. Domic has been involved in the organization of several technical conferences, including the Design Automation Conference (DAC), Design Automation & Test Europe (DATE), the International Conference on Computer-Aided Design (ICCAD), and the International Conference on Computer Design (ICCD). He participates frequently in industry panels regarding design and manufacturing technologies. Dr. Domic holds a B.S. in mathematics and electrical engineering from the University of Chile in Santiago, Chile, and a Ph.D. in mathematics from the Massachusetts Institute of Technology in Cambridge, Massachusetts.

TBD

Krishna Yarlagadda
President & CEO
HelloSoft

Abstract of keynote to be provided.

About Krishna Yarlagadda

As the President & CEO of HelloSoft, Krishna is responsible for setting HelloSoft's mission, formulating corporate strategy and executing a plan for the company's overall growth. Under Krishna's leadership, HelloSoft became market leader in wireless VoIP and related technologies. Prior to starting HelloSoft, Krishna was Chairman, President & CEO of ZSP, where he pioneered the development of DSP's based on RISC technology. ZSP was acquired by LSI Logic, and it's industry leading DSP architecture has been adopted by major semiconductor companies including Broadcom, IBM, Connexant, GlobespanVirata, Skyworks, Yamaha and PMC-Sierra. A seasoned entrepreneur, Krishna has been involved with several successful companies as investor, advisor or board member - nBand (acquired by Proxim), a communications processor company, Silicon Spice (acquired by Broadcom), vEngines (acquired by Centillium), Intoto (acquired by Freescale), Valyd (acquired by EMC) and eSilicon. Krishna held key management and technical positions in the SPARC processor division of Sun Microsystems and was a key player in successful launch of four SPARC processors (UltraSPARC I & II, SuperSPARC I & II). Krishna is a frequently invited speaker on DSP architecture and technology, and a contributor on DSP to industry journals such as Microprocessor report, Computer design, and EEtimes. Krishna has a B.S and MS in Electrical Engineering.

Design for eBeam : Getting the Best Wafers Without the Exploding Mask Cost

Aki Fujimura
CEO
D2S & eBeam Initiative

DFM (design for manufacturing) and RET (reticle enhancement technologies) have garnered much attention, highlighting the need for designers to consider the effects of the physics of light in the semiconductor manufacturing process. Largely ignored, but equally important are the effects of the physics of electron beams used both in ebeam direct write lithography and in ebeam mask writers. The talk discusses how important it is for designers to understand Design for eBeam.

About Aki Fujimura

Aki Fujimura is the Chairman and CEO of D2S, Inc. Previously, he was CTO of Cadence Design Systems. He helped Pure Software and Simplex Solutions become public companies in his tenures as inside board memebers. He was a co-founder of Tangent Design Systems where he defined DEF, LEF, and ECO which became standards in the area-based place and route. He has been on the board of HLDS, Bristol Technologies, R2, and S7 in addition to Pure and Simplex. He currently serves on the board of Coverity, Inc.

Cost-Aware System LSI Design

Steve Glaser
Corporate VP
Cadence Design Systems

Based on traditional cost factors, SoC design costs are forecast to approach 50-$100M for a single chip. Only in the very largest markets can a company gain an adequate return on that level of design cost. At the same time, there is a growth of package, test and IP royalty costs relative to die costs that must be managed to maintain adequate gross margins. Finally, with the time to market sensitive nature of consumer markets, companies are experiencing an unacceptable cost of delay.
Companies are seeking strategies to become ‘cost aware’ as they proceed with design and implementation, in order to meet their profitability goals. As a result, the largest companies are making internal investments in ad hoc, unconnected extensions to their design flows. Worse yet, many companies continue to drive blind with little hope of hitting cost and profitability targets.
There are specific best practices associated with managing unit costs. This starts with technical chip planning and IP evaluation combined with cost analysis. This is followed optimization techniques for die, test, packaging, and IP royalties coupled with tracking against the original chip and cost plan. To manage design costs, there are emerging best practices to develop, qualify and instrument IP in a way that makes it ‘integration ready’. This is followed by methods and automation to speed and lower the cost of SoC functional integration and verification, and implementation.
Glaser will show how a cost-aware approach addresses each of these challenges to manage costs and improve profitability, while delivering competitive products on schedules that are tighter than ever before.

About Steve Glaser

Steve Glaser is corporate vice president for strategy and planning at Cadence Design Systems, Inc. With twenty six years of experience in senior strategy, technical, marketing and business development roles, he has led major industry and corporate initiatives in SoC design, IP standards, system level design, and metric-driven verification for the systems, semiconductor and EDA industries. Prior to his current position, Mr. Glaser was corporate vice president of Marketing and Strategy for the Cadence Verification Division and senior vice president of Marketing and Strategy at Verisity Design. Prior to joining Verisity, Mr. Glaser was corporate vice president of Business Development and vice president of Strategic Marketing for Cadence. Mr. Glaser has also held various senior business and technical positions at the Alta Group of Cadence, Redwood Design, VLSI Technology, and Hughes Aircraft. Mr. Glaser received a Bachelor of Science degree in Electrical Engineering and Computer Science from the University of California, Santa Barbara, and a Masters degree in Business Administration from the University of British Columbia.