Intermittent computing systems (ImC) are a product of evolving edge devices. ImC is envisioned as a possible substitute for devices with consistent power and battery backup. However, the difficulties of an unreliable power supply, which causes frequent interruptions in task execution, prevent the widespread deployment of such systems. The need for creative architectural designs has resulted from this.
This paper proposes a new architecture for ImC that uses a level-1 volatile SRAM cache to minimize runtime interruptions and speed up task execution. There are speed and energy benefits to faster writing to SRAM caches. Furthermore, frequently written blocks are stored on a little STT scratchpad memory in case of evictions. On average, the system speeds up by 34%. Moreover, It reduces energy consumption by 46.89%. In addition, it achieves a 50% increase in forward progress compared to its equivalents and more than ~95\% reduction in backup overhead compared to a totally non-volatile design.