RTL integrations encounter many challenges due to IPs and logic residing on multi-voltage domains in SoCs. Design convergence may need frequent connectivity updates and power domain changes associated with interface logic. If such changes are distributed across physical and logical partitions, it will pose difficulties for design closure especially at the final stages of the design cycle. To minimize design efforts and cost, a global interface unit, which can house diverse digital logic, can be implemented. The proposed interface unit will house level-shifters, isolation cells, buffers for signal splitting, repeaters, glue logic etc., to cater to multi-voltage designs.