This manuscript investigates the effect of variations in temperature and Interface Trap Charges (ITC) on the analog and RF performance parameters of a Si/Ge heterojunction asymmetric double-gate dopingless TFET (HJ-ADG-DLTFET) with high-κ gate dielectric in terms of temperature and interface trap charges (ITC) of negative as well as positive polarity. The HJ-ADG-DLTFET employs a small bandgap material (i.e., Germanium) in the source region instead of Silicon. Consequently, increment in band-to-band tunneling (BTBT) and hence drive current at the source-channel tunneling junction, as the channel is made up of Silicon. The simulation is done by utilizing Silvaco ATLAS device simulator at various ITC density and polarity and for a broad temperature spectrum from 200 – 400 K. The results illustrate that higher PITC (Positive ITC) density degrades device performance enormously. Furthermore, temperature variations for the range from 200 – 400 K demonstrate the degradation of the off-state current of HJ-ADG-DLTFET.