This paper demonstrates performance enhancement with activated dummy fins based on a 12-nm FinFET technology definition for high-performance logic module design. The proposed scheme uses a double-height cell structure with two additional active fins enabled compared to traditional single-height cell stacking. The increase in total active fins in the proposed scheme results in higher effective transistor density and better cell performance. Through Design and Technology Co-Optimization, the parasitic capacitance of these proposed cells can be further decreased, with a NAND2x4 cell yielding 20% lower parasitic capacitance per fin compared to a traditional single-height cell. The proposed scheme shows the highest efficacy for gate-dominant and complex module designs like CPUs. The proposed scheme does not introduce any area penalty compared to conventional designs with single-height cells.