Logic encryption is a potential solution to the ever-increasing problem of IP piracy and counterfeiting. However, most of the logic encryption techniques are vulnerable to the powerful SAT attack. One possible way to prevent SAT attack on sequential circuits is to restrict the controllability and observability of the internal states of the flip-flop by obfuscating the scan operation. However, a recent attack called ScanSAT can break these scan obfuscation guided defense mechanisms. In this paper, we propose to integrate a lightweight test authentication mechanism with such baseline SAT preventive strategies, which enables us to withstand the threat of the ScanSAT attack. We have shown the strength of our approach by integrating it with \textit{Encrypt Flip-Flop}, a recent scan obfuscation guided SAT preventive approach. The proposed approach not only protects the IP of the design but also offers protection against scan-based side-channel attacks at a much lower cost compared to the existing methods.