In this paper, we present an efficient statistical approach for analyzing the robustness of threshold logic gates in the presence of process variations and using the results of that analysis to tune the weights of the threshold gate to maximize yield. Although the proposed methodology is completely general and can be applied to any circuit (digital, mixed-signal or analog), we demonstrate it using a flash transistor based threshold logic gate. We have chosen this implementation because of the readily available MOSFET and flash transistor device models for simulation in SPICE. The statistical approach presented in this paper involves construction of an efficient database and the design of a stochastic simulator based on an extension to polynomial chaos technique. The results demonstrate that this methodology when using the stochastic simulator achieves maximum speed up of 56.5X in reducing the HSPICE iterations while maintaining the accuracy.