This paper demonstrates a PLL compiler which gen- erates GDS data from performance specification. Pulse Width controlled PLL (PWPLL) architecture is suitable for a digital- flow PLL design, and there are 8 design parameters in PWPLL, such as the number of stages of the ring oscillator. The inputs for our PLL compiler are standard cell library, SPICE parameters and the target specification file defining the input reference frequency, output PLL frequency and the corner conditions of TYP/BEST/WORST and other PVT conditions. Then the PLL compiler calculates rough values of the 8 design parameters, runs SPICE simulations, analyzes the waveform files to adjust the design parameters, and finally generates the gate-level verilog netlist that can be used for the commonly used digital circuit design flow, such that the PLL compiler generates scripts for a commercial digital tool chain of P&R, verification (LVS/DRC) and RC extraction tools, and invokes the tools with the scripts to generate the final GDS, and confirms that the compiled PLL locks under the given corner conditions by using SPICE simulation.