Session 6C

San Martin Room

1:00pm - 3:05pm

DSM Interconnect Issues

Chairs:    Farzan Fallah, Fujitsu Laboratories of America

Norman Chang, Apache Design Solutions

1:00pm

Introduction

1:05pm

6C.1       

Current Calculation on Signal Interconnects

Muzhou Shao, Youxin Gao, Lipen Yuan, Martin Df Wong, Hungming Chen, Synopsys Inc.

1:35pm

6C.2       

Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills

Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Chang Wei Fong, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda, STARC Japan

2:05pm

6C.3       

Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits

Vinita V. Deodhar, Jeffrey A. Davis, Georgia Institute of Technology

2:35pm

6C.4       

Interconnect Delay and Slew Metrics Using the First Three Moments

Jiaxing Sun, Yun Zheng, Qing Ye, Tianchun Ye

2:50pm

6C.5       

Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits

Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan, University of California Riverside