Session 4A
10:30am
- 12:00pm
James
Lei, Altera
Kris Verma, Seagate
10:30am
Introduction
10:35am
4A-1
A Sensitivity Based
Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects
Medha Kulkarni and Tom Chen
11:05am
4A-2
Analytical
Dynamic Time Delay Model of Strongly Coupled RLC Interconnect Lines Dependent on
Switching
Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, and Jongin Shim
11:35am
4A-3
A Scalable
Communication-Centric SoC Interconnect Architecture
Cristian Grecu, Partha Pratim Pande, Andre Ivanov, Res Saleh
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