Tutorial Track D

Design flows and methodologies

Chair and moderator:

Tutorial D1

08:30am – 10:15am

nVHDL: A Hardware Design Language for Modeling Discrete and Analog Design

and Simulation of Mixed-Signal Electronic Systems

Organizer & Presenter:         Sumit Ghosh, Stevens Institute of Technology

The tutorial will focus on the fundamental principles and concepts that underlie every hardware description language invented to-date. It will begin with a quick survey of the classical HDLs for digital systems, discuss Verilog, and then focus heavily on VHDL. HDLs for analog systems such as VHDL-AMS and their basic weaknesses, starting from the fundamental requirements of mixed-signal electronic designs will be examined. Next, the tutorial will concentrate, through meaningful and real-world examples, on how to accurately model hardware so as to get reliable results from HDL simulations. The issues of concurrent simulation of VHDL models on parallel processors and new transport delay semantics that will enable the modeling of PCI and other sophisticated buses based on electromagnetic reflections will be addressed. Finally, in the tutorial, the present problems with VHDL will be examined and current research in “mixed signal” modeling and simulation, that may constitute the basis for a future evolution in HDL technology, namely nVHDL will be reviewed. Time permitting, the tutorial will also explain how to design HDL simulators.

Tutorial D2

10:30am – 12:15pm

Platform-Based Design: A tutorial

Organizer:         Grant Martin, Cadence Design Systems

Presenters:        Grant Martin, and Henry Chang Cadence Design Systems

This tutorial is an introduction and overview of platform-based design and its key issues. First, the concept will be defined and the platform taxonomy will be illustrated with a number of industrial examples. A brief overview of the basic methodology elements involved in platform-based design will be given. This will concentrate on the key differences from hardware-based design flows: system-level design and embedded software. Finally, key emerging areas in platform-based design, including co-design across design disciplines, the rise of AMS SOCs, and the opportunities offered by emerging programmable fabrics will be discussed.

Tutorial D3

1:30pm – 3:15pm

Quality Aspects of SOI Circuit Design

Organizer & Presenter:         Andrew Marshall, Texas Instruments, Inc.

This tutorial focuses on challenges of SOI design and test. With the switch from bulk to SOI, combined with technology scaling, new issues are being raised about IC quality and reliability. Design and testing techniques for ICs built on SOI material are explained. This tutorial covers the following topics: Basic analog, digital and memory design techniques for SOI applications. Floating body effects. Differences between design of SOI and bulk – active and passive component performance. Low-voltage low-power SOI CMOS design style, Cross-talk and local heating issues, Simulation of SOI designs, layout techniques for SOI, Testing of SOI circuits to ensure quality product.

Tutorial D4

3:30pm – 5:15pm

Optimization in an Integrated Physical Design Flow

Organizer & Presenter         Olivier Coudert, Monterey Design Systems, Inc.

The purpose of a physical design flow is to take a netlist with a set of constraints (timing, area, power, etc.), and to produce a production worthy layout. This cannot be achieved without considering all the interdependencies between placement, timing, logic optimization, routing, etc. Traditional optimization methods that have been used more or less independently: for example, placement optimization did not interact with logic optimization. Today's need for integrated physical design flows requires these methods to be more "educated" about each other and to work simultaneously. This tutorial will present a physical design flow and describe how different optimization methods (placement, logic, routing) cooperate together.