Tutorial Track B

Design for reliability in UDSM: Issues and solutions

Chair and moderator:

Tutorial B1

08:30am – 10:15am

ESD Protection Design Methods for Deep Submicron Technologies

Organizer & Presenter:        Charvaka Duvvury, Texas Instruments, Inc.

Electrostatic Discharge (ESD) has been one of the major reliability concerns for IC technologies. In the development of protection circuits against ESD the role of the designers is becoming increasingly important. This tutorial will address the important issues for the design of IC protection circuits built with state-of-the-art deep submicron technologies. The tutorial will present the fundamental aspects of the ESD protection design as well as the latest novel clamps. The effects of process technologies on the protection device performance and the effective choice of the protection scheme for different design applications, including RF circuits, will be discussed. In addition to low voltage CMOS, SOI, BiCMOS, and High Voltage MOS will also be considered.  All aspects of the current design techniques and the simulation methods to optimize the protection schemes will be discussed. Finally, the CAD tools available for ESD design will be reviewed.

Tutorial B2

10:30am – 12:15pm

Electromigration Reliability Issues in High-Performance Circuit Designs

Organizer & Presenter:      J. Joseph Clement, Sandia National Laboratories

This tutorial aims to provide circuit designers, CAD and reliability engineers with a common framework they can use in order to achieve the desired circuit performance and reliability goals. The first part of this tutorial will start with a review of the physical mechanisms underlying the electromigration phenomenon, the driving forces, and the effects of the thin-film metal material properties and the surrounding insulating dielectric. Next common accelerated testing procedures and the model generally used to extrapolate test results to predict interconnect lifetimes will be presented. The relationship between constant current life tests and the pulsed currents found in an operating circuit environment will be addressed. The second part of the tutorial will focus on design procedures and CAD tools that can be used to assess and assure the electromigration reliability of a circuit design. The concept of a "reliability budget" will be introduced.  Finally, promising directions for future work will be explored.

Tutorial B3

1:30pm – 3:15pm

Ultra-Thin Gate Oxide Reliability and Implications for Design

Organizer & Presenter:         John S. Suehle, National Institute of Standards and Technology

New observations of a voltage dependent voltage acceleration parameter and non-Arrhenius temperature dependence will be presented. The current understanding of soft breakdown will be discussed and proposed techniques for detecting breakdown presented. The implications of soft breakdown on circuit functionality and the applicability of applying current reliability characterization and analysis techniques to project the reliability of future alternative gate dielectrics will be discussed. An overview of past and present thin oxide reliability characterization techniques will be presented. A special emphasis will be placed on issues relating to the characterizing and understanding of breakdown in current technology ultra-thin gate oxides where excessive tunneling currents and soft breakdown complicate reliability assessment.

Tutorial B4

3:30pm – 5:15pm

Hot Carrier Reliability and Design Considerations

Organizer & Presenter:         Shian Aur, Texas Instruments, Inc.

In this tutorial, hot carrier effects will be first demonstrated using device I-V characteristics before and after DC stress. Then, the hot carrier mechanism will be reviewed and the hot carrier lifetime prediction methodology be discussed. In circuit operation, device is under AC stress. The circuit hot carrier effects will be discussed in an inverter example. Then, a three-stage inverter chain will be demonstrated to compare the DC and AC stress cases. In real circuits, the circuit performance degradation is the concern, not necessarily the individual transistors. The circuit hot carrier simulator (HOTRON) is used to discuss several circuit examples. The mechanism in HOTRON simulator will be discussed. Some design guidelines for checking the circuit design reliability will be provided.