Session 4A

3:30pm – 5:15pm

Low Power Design Tecniques

Co-Chairs: 

Vivek De, Intel Corporation

Michael Zelikson, IBM

3:35pm

4A-1

Low-Power and High-Speed VLSI Design with Low Supply Voltage Through Cooperation Between Levels (Invited), Takayasu Sakurai, University of Tokyo, Tokyo, Japan

4:00pm

4A-2

Does Q=MC2? (On the Relationship Between Quality in Electronic Design and the Model of Colloidal Computing) (Invited), Radu Marculescu and Diana Marculescu, Carnegie Mellon University, Pittsburgh, PA

4:25pm

4A-3

Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications, Geun Rae Cho, Tom Chen, Colorado State University, Fort Collins, CO

4:50pm

4A-4

Structural Decomposition with Functional Considerations for Low Power, Chih-Hung Lee, Yu-Chung Lin, Hsin-Hsiung Huang, and Tsai-Ming Hsieh, Chung-Yuan Christian University, Chung-Li, Taiwan

5:15pm

4A-5

ALBORZ: Address Level Bus Power Optimization, Yasdan Aghaghiri, Farzan Fallah² and Massoud Pedram, University of Southern California, Los Angeles, CA and ²Fujitsu Labs of America, Sunnyvale, CA